IEEE Std 1076-2008 VHDL 语言参考手册

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"1076-2008 IEEE Standard VHDL. Language Reference Manual (z-lib.org).pdf" 本文档是IEEE Std 1076-2008，即2008年修订版的IEEE标准VHDL语言参考手册。VHDL（Very High Speed Integrated Circuit Hardware Description Language）是一种广泛使用的硬件描述语言，用于设计和建模数字系统，特别是在集成电路和可编程逻辑器件的设计中。这个标准由IEEE Computer Society的Design Automation Standards Committee赞助，并于2008年9月26日获得IEEE-SA Standards Board的批准。 VHDL语言参考手册提供了关于VHDL语法、语义和用法的全面信息。它详细介绍了语言的各种元素，包括数据类型、运算符、流程控制结构、实体、架构、包、库、过程、函数、信号、组件等。这些元素构成了VHDL的核心，使得设计者可以精确地描述硬件行为和结构。在该手册中，读者可以找到以下关键知识点： 1. **数据类型**：VHDL支持基本数据类型（如BIT、BOOLEAN、INTEGER、REAL等），用户定义的数据类型以及标准库中的类型（如STD_LOGIC和STD_LOGIC_VECTOR）。 2. **运算符**：包括算术运算符（+、-、*、/、MOD）、关系运算符（=、/=、<、>、<=、>=）、逻辑运算符（AND、OR、NOT、XOR）以及位操作运算符。 3. **程序结构**：VHDL提供进程（PROCESS）、函数（FUNCTION）和过程（PROCEDURE）来实现控制流。进程是并发执行的实体，可以包含敏感列表、变量声明和顺序语句。 4. **实体和架构**：实体描述了硬件接口，而架构则定义了实体的行为和结构。架构可以是行为的，模拟系统的功能，也可以是结构的，映射到具体的硬件。 5. **库和包**：库用于组织VHDL实体和包，而包则包含相关的类型、常量、信号和子程序声明，提高了代码的复用性和组织性。 6. **信号**：VHDL中的信号用来模拟硬件的并行通信，它们可以在进程之间传递信息，并且有延迟特性。 7. **配置**：配置用于指定设计实体的实例化和其内部结构的连接，提供了更灵活的复用和定制能力。 8. **模拟和综合**：VHDL代码可以被仿真工具用于验证设计的功能正确性，也可以被综合工具转换为具体的门级电路描述，供FPGA或ASIC实现。 9. **标准库**：IEEE库（如IEEE.STD_LOGIC_1164）包含预定义的数据类型、组件和函数，简化了设计工作。 10. **设计层次**：VHDL支持从高层次的系统级描述到低层次的门级描述的无缝设计流程，这使得设计者能够从宏观到微观地理解并优化系统。这个标准文档对于理解和使用VHDL进行数字系统设计至关重要，无论是初学者还是经验丰富的工程师，都可以从中受益。通过深入学习VHDL，设计者可以更好地掌握现代电子设计自动化流程，提高设计效率和质量。

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IEEE STANDARD VHDL LANGUAGE REFERENCE MANUAL Std 1076-2008

f) Braces { } enclose a repeated item or items on the right-hand side of a production. The items may

appear zero or more times; the repetitions occur from left to right as with an equivalent left-recursive

rule. Thus, the following two productions are equivalent:

term ::= factor { multiplying_operator factor }

term ::= factor | term multiplying_operator factor

g) If the name of any syntactic category starts with an italicized part, it is equivalent to the category

name without the italicized part. The italicized part is intended to convey some semantic informa-

tion. For example, type_name and subtype_name are both syntactically equivalent to name alone.

h) The term simple_name is used for any occurrence of an identifier that already denotes some

declared entity.

1.3.3 Semantic description

The meaning and restrictions of a particular construct are described with a set of narrative rules immediately

following the syntactic productions. In these rules, an italicized term indicates the definition of that term,

and identifiers appearing entirely in uppercase letters refer to definitions in package STANDARD (see

16.3).

The following terms are used in these semantic descriptions with the following meanings:

erroneous: The condition described represents an ill-formed description; however, implementations are not

required to detect and report this condition. Conditions are deemed erroneous only when it is impossible in

general to detect the condition during the processing of the language.

error: The condition described represents an ill-formed description; implementations are required to detect

the condition and report an error to the user of the tool.

illegal: A synonym for “error.”

legal: The condition described represents a well-formed description.

1.3.4 Front matter, examples, notes, references, and annexes

Prior to this subclause are several pieces of introductory material; following Clause 24 are some annexes and

an index. The front matter, annexes (except Annex B), and index serve to orient and otherwise aid the user

of this standard, but are not part of the definition of VHDL; Annex B, however, is normative.

Some clauses of this standard contain examples, notes, and cross-references to other clauses of the standard;

these parts always appear at the end of a clause. Examples are meant to illustrate the possible forms of the

construct described. Illegal examples are italicized. Notes are meant to emphasize consequences of the rules

described in the clause or elsewhere. In order to distinguish notes from the other narrative portions of this

standard, notes are set as enumerated paragraphs in a font smaller than the rest of the text. Cross-references

are meant to guide the user to other relevant clauses of the standard. Examples, notes, and cross-references

are not part of the definition of the language.

1.3.5 Incorporation of Property Specification Language

VHDL incorporates the simple subset of the Property Specification Language (PSL) as an embedded

language for formal specification of the behavior of a VHDL description. PSL is defined by

IEEE Std 1850

-2005.

All PSL constructs that appear in a VHDL description shall conform to the

Information on references can be found in Clause 2.

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IEEE STANDARD VHDL LANGUAGE REFERENCE MANUAL Std 1076-2008

2. Normative references

The following referenced documents are indispensable for the application of this document (i.e., they must

be understood and used, so each referenced document is cited in text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of

the referenced document (including any amendments or corrigenda) applies.

IEEE Std 754

-1985 (Reaff 1990), IEEE Standard for Binary Floating-Point Arithmetic.

IEEE Std 854

-1987 (Reaff 1994), IEEE Standard for Radix-Independent Floating-Point Arithmetic.

IEEE Std 1850

-2005, IEEE Standard for Property Specification Language (PSL).

ISO/IEC 8859-1:1998, Information technology—8-bit single-byte coded graphic character sets—Part 1:

Latin alphabet No. 1.

ISO/IEC 9899:1999, Programming languages—C.

ISO/IEC 9899:1999/Cor 1:2001, Programming languages—C, Technical Corrigendum 1.

ISO/IEC 9899:1999/Cor 2:2004, Programming languages—C, Technical Corrigendum 2.

ISO/IEC 19501:2005, Information technology—Open Distributed Processing—Unified Modeling Language

(UML) Version 1.4.2.

IEEE publications are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, P.O. Box 1331, Piscataway,

NJ 08855-1331, USA (http://standards.ieee.org/).

The IEEE standards or products referred to in this clause are trademarks of the Institute of Electrical and Electronics Engineers, Inc.

ISO/IEC publications are available from the ISO Central Secretariat, Case Postale 56, 1 rue de Varembé, CH-1211, Genève 20, Swit-

zerland/Suisse (http://www.iso.ch/). ISO/IEC publications are also available in the United States from Global Engineering Documents,

15 Inverness Way East, Englewood, Colorado 80112, USA (http://global.ihs.com/). Electronic copies are available in the United States

from the American National Standards Institute, 25 West 43rd Street, 4th Floor, New York, NY 10036, USA (http://www.ansi.org/).

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IEEE STANDARD VHDL LANGUAGE REFERENCE MANUAL Std 1076-2008

3. Design entities and configurations

3.1 General

The design entity is the primary hardware abstraction in VHDL. It represents a portion of a hardware design

that has well-defined inputs and outputs and performs a well-defined function. A design entity may

represent an entire system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of abstraction

in-between. A configuration can be used to describe how design entities are put together to form a complete

design.

A design entity may be described in terms of a hierarchy of blocks, each of which represents a portion of the

whole design. The top-level block in such a hierarchy is the design entity itself; such a block is an external

block that resides in a library and may be used as a component of other designs. Nested blocks in the

hierarchy are internal blocks, defined by block statements (see 11.2).

A design entity may also be described in terms of interconnected components. Each component of a design

entity may be bound to a lower-level design entity in order to define the structure or behavior of that

component. Successive decomposition of a design entity into components, and binding those components to

other design entities that may be decomposed in like manner, results in a hierarchy of design entities

representing a complete design. Such a collection of design entities is called a design hierarchy. The

bindings necessary to identify a design hierarchy can be specified in a configuration of the top-level entity in

the hierarchy.

This clause describes the way in which design entities and configurations are defined. A design entity is

defined by an entity declaration together with a corresponding architecture body. A configuration is defined

by a configuration declaration.

3.2 Entity declarations

3.2.1 General

An entity declaration defines the interface between a given design entity and the environment in which it is

used. It may also specify declarations and statements that are part of the design entity. A given entity

declaration may be shared by many design entities, each of which has a different architecture. Thus, an

entity declaration can potentially represent a class of design entities, each with the same interface.

entity_declaration ::=

entity identifier is

entity_header

entity_declarative_part

[ begin

entity_statement_part ]

end [ entity ] [ entity_simple_name ] ;

The entity header and entity declarative part consist of declarative items that pertain to each design entity

whose interface is defined by the entity declaration. The entity statement part, if present, consists of

concurrent statements that are present in each such design entity.

If a simple name appears at the end of an entity declaration, it shall repeat the identifier of the entity

declaration.

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