PIC12F683微控制器数据手册：高性能RISC CPU与低功耗特性

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"12F683 datasheet" 12F683是一款高性能的RISC（精简指令集计算机）CPU，专为微控制器应用设计。它具有以下主要特点： 1. **指令集**: 该芯片有35条简单的指令，其中大部分指令在一个时钟周期内完成，包括除跳转指令之外的其他指令。这使得程序执行效率高且易于学习。 2. **工作速度**: 它可以在直流到20MHz的振荡器/时钟频率下工作，对应指令周期为直流到200ns。这种广泛的频率范围适应了不同应用场景的需求。 3. **中断功能**: 12F683提供8级深的硬件堆栈，支持中断处理，适合实时系统的需求。 4. **内部振荡器**: 集成了高精度、出厂校准过的±1%精度内部振荡器。用户可以通过软件选择31kHz到8MHz的工作频率，还具备双速启动和晶振故障检测功能，确保在关键应用中的可靠性。 5. **节能模式**: 支持节能休眠模式，能在低至2.0V到5.5V的宽工作电压范围内工作。同时，芯片在节能模式下可以切换时钟模式，并且有上电复位（POR）、上电延时定时器（PWRT）和振荡器起振定时器（OST）等功能。 6. **复位功能**: 上拉/输入引脚复用的主复位功能增强了系统的稳定性和安全性。 7. **代码保护**: 提供可编程的代码保护，确保代码的安全性。高耐用性闪存和EEPROM单元可以承受多次写入操作，而数据保存时间超过40年。 8. **低功耗**: 待机电流典型值仅为1nA，工作电流在不同频率和电压下有不同典型值，例如在32kHz和2.0V下为8.5µA，在1MHz和2.0V下为100µA。此外，看门狗定时器电流典型值为1µA。 9. **I/O特性**: 6个独立方向控制的I/O引脚，能直接驱动LED，支持引脚电平变化中断和独立的可编程弱上拉。GP0引脚还有超低功耗唤醒功能。 10. **模拟和数字外设**: 包括一个模拟比较器，带可编程片上参考电压模块，以及10位A/D转换器。Timer0是8位定时器/计数器，Timer1是增强型16位定时器/计数器，Timer2带有8位周期寄存器等。还有捕捉、比较和PWM模块，支持多种功能。 11. **在线编程**: 通过In-Circuit Serial Programming (ICSP)技术，可以在系统中对芯片进行串行编程，方便调试和更新。请注意，该文档由Microchip Technology Inc.发布，提供给用户参考，但不保证信息的准确性和适用性。用户需自行确认应用是否满足其规格要求。使用Microchip的器件在生命支持和安全应用中完全由购买者承担风险。在使用中可能出现的任何损害，Microchip不承担法律责任。

PIC12F683

2.2.2.4 PIE1 Register

The PIE1 register contains the interrupt enable bits, as

shown in Register 2-4.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt

0 = Disables the ADC interrupt

bit 5 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 4 Unimplemented: Read as ‘0’

bit 3 CMIE: Comparator Interrupt Enable bit

1 = Enables the Comparator 1 interrupt

0 = Disables the Comparator 1 interrupt

bit 2 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the oscillator fail interrupt

0 = Disables the oscillator fail interrupt

bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt

0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt

0 = Disables the Timer1 overflow interrupt

PIC12F683

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-5.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation has not completed or has not been started

bit 6 ADIF: A/D Interrupt Flag bit

1 = A/D conversion complete

0 = A/D conversion has not completed or has not been started

bit 5 CCP1IF: CCP1 Interrupt Flag bit

Capture mod

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode

Unused in this mode

bit 4 Unimplemented: Read as ‘0’

bit 3 CMIF: Comparator Interrupt Flag bit

1 = Comparator 1 output has changed (must be cleared in software)

0 = Comparator 1 output has not changed

bit 2 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0 = System clock operating

bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

1 = Timer2 to PR2 match occurred (must be cleared in software)

0 = Timer2 to PR2 match has not occurred

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Timer1 register overflowed (must be cleared in software)

0 = Timer1 has not overflowed

PIC12F683

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from PCLATH.

On any Reset, the PC is cleared. Figure 2-3 shows the

two situations for the loading of the PC. The upper

example in Figure 2-3 shows how the PC is loaded on a

write to PCL (PCLATH<4:0> → PCH). The lower exam-

ple in Figure 2-3 shows how the PC is loaded during a

CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When perform-

ing a table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block). Refer to the

Application Note AN556, “Implementing a Table Read”

(DS00556).

2.3.2 STACK

The PIC12F683 family has an 8-level x 13-bit wide

hardware stack (see Figure 2-1). The stack space is

not part of either program or data space and the Stack

Pointer is not readable or writable. The PC is PUSHed

onto the stack when a CALL instruction is executed or

an interrupt causes a branch. The stack is POPed in

the event of a RETURN, RETLW or a RETFIE instruction

execution. PCLATH is not affected by a PUSH or POP

operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

2.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit of

the STATUS register, as shown in Figure 2-4.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

12 8 7 0

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE<10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interrupt address.

MOVLW 0x20 ;initialize pointer

MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer

BTFSS FSR,4 ;all done?

GOTO NEXT ;no clear next

CONTINUE ;yes continue

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