2.7-Gb/s 自动频率获取 CDR 时钟恢复电路

4星 · 超过85%的资源需积分: 41 197 浏览量更新于2024-09-11 6 收藏 1.78MB PDF 举报

"本文介绍了CDR（Clock and Data Recovery，时钟和数据恢复）集成电路，特别是一种能在12.5 Mb/s至2.7 Gb/s范围内连续速率工作的CDR电路。该电路具备自动频率获取和数据速率读回功能，无需外部参考时钟或编程即可在输入数据率改变时进行调整。在2.5 Gb/s速率下，其获取时间仅为1毫秒。在跟踪模式下，采用双DLL（Delay Line Loop，延迟线环路）/PLL（Phase-Locked Loop，相位锁定环路）结构，提供优于标准二阶环路的抖动性能。在OC48数据速率下，实现了500 kHz的抖动传递带宽和3 MHz的抖动容限带宽。该电路采用0.35微米双多晶硅、三层金属（DPTM）BiCMOS工艺制造，3.3 V电源下功耗为235 mA，占用面积为9平方毫米，适用于光纤通信和光纤到户系统，如交换机等应用。" CDR（时钟和数据恢复）电路是光纤通信系统中的关键组件，它的主要任务是在接收端恢复出数据传输过程中的原始时钟信号。本摘要介绍的是一种能够处理不同速率数据流的CDR电路，其工作范围广泛，覆盖了从低速到高速的数据传输需求，最大可达到2.7 Gb/s。这一特性使得该电路具有很强的适应性，能应对不同网络环境下的数据传输。自动频率获取功能使得该CDR电路能够在输入数据速率发生变化时自动调整，无需依赖外部参考时钟，简化了系统设计。同时，它还能够向用户反馈当前的数据速率，这对于系统的监控和调试十分有用。在2.5 Gb/s的高速运行环境下，该电路的快速频率获取时间为1毫秒，确保了数据的及时和准确恢复。在跟踪模式下，采用的双DLL/PLL结构能够有效地减少由于信号传输过程中的噪声和抖动所导致的错误，提高了系统的稳定性和可靠性。500 kHz的抖动传递带宽和3 MHz的抖动容限带宽指标表明，该电路在抑制和过滤抖动方面表现出色，保证了数据传输的高质量。此外，电路的低功耗设计（235 mA，3.3 V）和小体积（9 mm2）对于集成到现代光纤通信设备，如光纤到户（FTTH）和交换机等应用中，是非常理想的。0.35微米的双多晶硅、三层金属的BiCMOS工艺技术则提供了良好的工艺兼容性和成本效益。这种连续速率的CDR电路是光纤通信领域的一个重要突破，它通过其高效、灵活和高性能的特点，对提高系统整体性能和稳定性起到了关键作用。

DALTON et al.: CONTINUOUS-RATE CDR WITH AUTOMATIC FREQUENCY ACQUISITION AND DATA-RATE READBACK 2715

Fig. 4. Small-signal model of D/PLL.

model of Fig. 3. First, JTRAN is given by the overall transfer

function from input to output,

(1)

This displays the required low-pass response and starts to roll

off at the higher of the two closed-loop poles given by

(2)

since the closed-loop zero

and the ﬁrst closed-loop pole

practically cancel. Exact cancellation, however, would re-

quire inﬁnite loop gain and the extent to which the zero and pole

do not cancel leads to peaking (JPEAK) in the transfer function

where the gain is greater than one. This is unavoidable with this

architecture but can be minimized by using a large loop ﬁlter

capacitor.

The JTOL performance can be evaluated by deriving the

transfer function,

. is the phase error between

the input data and the recovered clock. If this error exceeds a

certain limit, a retiming error will occur. The circuit displays

a high-pass function from

to , which means that

low-frequency jitter appearing at the input,

, is greatly

attenuated at

, which, in turn, means that large amounts

of low-frequency jitter can be tolerated. The JTOL is then

inversely proportional to

, which is plotted in Fig. 3

and given by

(3)

This shows the expected high-pass response with the JTOL

corner frequency below which tolerance starts to improve, given

again by

. Above this high-pass corner frequency, the error

transfer is unity and so only small amounts of high-frequency

jitter may be tolerated before retiming errors are committed.

In practice, the high-frequency JTOL is determined by the fol-

lowing: static phase error in the PLL; eye closure in the input

data signal; and jitter generation in the PLL. These details are

beyond the scope of this paper and will not be further developed

here.

The problems with this architecture are now apparent. First,

good JTRAN performance requires a narrowband PLL, while

good JTOL performance requires a wideband PLL, but the

JTRAN and JTOL corner frequencies are both set by

making it difﬁcult to meet both speciﬁcations simultaneously.

For example, for the OC48 data rate, the SONET standard calls

for a JTRAN corner frequency of 2 MHz and a JTOL corner

frequency of 1 MHz, which means that the PLL bandwidth

must be maintained between these values over all conditions

of process, voltage, and temperature (PVT). Second, because

the closed-loop zero occurs before the ﬁrst closed-loop pole,

JPEAK greater than 0 dB is unavoidable.

III. D

ELAY- AND PHASE-LOCKED LOOP (D/PLL)

The D/PLL architecture [2] provides signiﬁcant performance

improvement over the standard second-order loop. Fig. 4 shows

a small-signal model. It consists of two loops: 1) a PLL con-

sisting of a PD and a CP with a combined gain of

[A/rad],

a loop ﬁlter implemented with a single capacitor

and a VCO

with a gain

[rad/Vs]; and 2) a delay-locked loop (DLL) that

shares the PD and CP with the PLL and also has a phase shifter

(PSH) with a gain of

[rad/V] in the loop. The PLL is a

second-order loop with narrow bandwidth, while the DLL is

a ﬁrst-order loop with much wider bandwidth. This architec-

ture is developed in [2], which focuses on the jitter transfer per-

formance and phase/frequency acquisition time. In this paper,

we focus on the following: the decoupling of the jitter transfer

and jitter tolerance corner frequencies; implementing a contin-

uous-rate CDR with this architecture; and, ﬁnally, incorporating

a frequency-locked loop (FLL) for wideband operation.

剩余12页未读，继续阅读

u011370053

粉丝: 1
资源: 1

2.7-Gb/s 自动频率获取 CDR 时钟恢复电路

通信与网络中的时钟与数据恢复（CDR）技术在高速串行通信链路中的应用

数据时钟恢复(CDR)工作原理及Altera的ASI、SDIIPcore应用.pdf

HASS试验对CDR的PPM容忍度要求

时钟恢复电路

EDA/PLD中的时钟恢复电路的Multisim仿真

时钟数据恢复电路_CDR_专利技术分析_王敏.pdf

cdr时钟恢复原理组成

cdr时钟数据恢复原理

时钟数据恢复(cdr) 电路

电子功用-时钟数据恢复电路及其方法

最新资源