AMD HD 6900系列指令集架构参考指南

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AMD HD 6900系列显卡是AMD公司在2011年推出的一款高性能GPU产品，它遵循了当时先进的AMD Accelerated Parallel Processing（APu）架构。这款显卡专为满足专业级图形处理需求而设计，特别强调在游戏、3D渲染、视频编辑等领域的出色性能。 HD 6900系列的Instruction Set Architecture (ISA)是其技术核心，它基于AMD的图形处理器设计语言，旨在提供高效的并行计算能力。这一架构采用了多核心技术，包括流处理器、纹理单元、光栅化引擎和内存控制器，使得图像处理任务能够并行化处理，从而提升整体性能。在硬件规格上，HD 6900系列可能包括了多个型号，如Radeon HD 6970、Radeon HD 6950等，每个型号都有不同的核心频率、显存容量和带宽，以适应不同级别的用户需求。这些显卡通常支持DirectX 11或更高版本，以及OpenGL标准，能够兼容Microsoft的Visual Studio开发环境，使得开发者可以利用高性能图形硬件进行高效的游戏开发和图形应用优化。值得注意的是，AMD HD 6900系列的开发过程中参考了微软的Windows Vista操作系统，并且利用了OpenCL技术，这是一种跨平台的并行计算框架，允许开发者编写一次代码并在多种设备上运行，包括CPU、GPU和FPGA等。Khronos组织授权AMD使用OpenCL商标，体现了AMD在GPU计算能力方面的开放性与兼容性。然而，AMD对文档内容的使用保留了所有权利，意味着可能会有更新或修改，用户在购买和使用时需留意官方发布的最新规格和驱动程序。同时，AMD强调了文档内容的预发布性质，可能会包含初步或高级特性，因此实际的产品表现可能会有所调整。 AMD HD 6900系列是一款具有强大图形处理能力的显卡，它在图形渲染、游戏性能和并行计算方面提供了卓越的解决方案，同时支持最新的编程接口和技术标准，对于追求高性能和开发者的用户来说是一个理想的选择。

AMD HD 6900 SERIES TECHNOLOGY

1-2

A host application cannot write to the HD 69XX device memory directly, but it can

command the HD 69XX device to copy programs and data between system

memory and device memory. For the CPU to write to GPU memory, there are

two ways:

• Request the GPU’s DMA engine to write data by pointing to the location of

the source data on CPU memory, then pointing at the offset in the GPU

memory.

• Upload a kernel to run on the shaders that access the memory through the

PCIe link, then process it and store it in the GPU memory.

In the HD 69XX environment, a complete application includes two parts:

• a program running on the host processor, and

• programs, called kernels, running on the HD 69XX processor.

The HD 69XX programs are controlled by host commands, which

• set HD 69XX internal base-address and other configuration registers,

• specify the data domain on which the HD 69XX GPU is to operate,

• invalidate and flush caches on the HD 69XX GPU, and

• cause the HD 69XX GPU to begin execution of a program.

The HD 69XX driver program runs on the host.

The DPP array is the heart of the HD 69XX processor. The array is organized

as a set of compute unit pipelines, each independent from the others, that

operate in parallel on streams of floating-point or integer data. The compute unit

pipelines can process data or, through the memory controller, transfer data to, or

from, memory. Computation in a compute unit pipeline can be made conditional.

Outputs written to memory can also be made conditional.

Host commands request a compute unit pipeline to execute a kernel by passing

it:

• an identifier pair (x, y),

• a conditional value, and

• the location in memory of the kernel code.

When it receives a request, the compute unit pipeline loads instructions and data

from memory, begins execution, and continues until the end of the kernel. As

kernels are running, the HD 69XX hardware automatically fetches instructions

and data from memory into on-chip caches; HD 69XX software plays no role in

this. HD 69XX software also can load data from off-chip memory into on-chip

general-purpose registers (GPRs) and caches.

Conceptually, each compute unit pipeline maintains a separate interface to

memory, consisting of index pairs and a field identifying the type of request

(program instruction, floating-point constant, integer constant, boolean constant,

input read, or output write). The index pairs for inputs, outputs, and constants are

AMD HD 6900 SERIES TECHNOLOGY

AMD HD 6900 Series Instruction Set Architecture 2-1

Chapter 2

Program Organization and State

HD 69XX programs consist of control-flow (CF) instructions, ALU instructions,

instructions for fetches through a texture cache, and exports. ALU instructions

can have up to three source operands and one destination operand. The

instructions operate on 32-bit or 64-bit IEEE floating-point values and signed or

unsigned integers. The execution of some instructions cause predicate bits to be

written that affect subsequent instructions. Programs typically use instructions for

fetching through a texture cache for data loads.

2.1 Program Types

The following program types are commonly run on the HD 69XX GPU (see

Figure 1.2, on page 1-4):

• Hull Shader (HS)— Receives patch data and processes it to generate new

patch data along with some constant data and tesselation factors.

• Domain Shader (DS)— Fetches HS output and constant data to compute the

vertex value based on U,V data from the tessellation engine. The tessellation

engine generates U,V coordinates based on tessellation factors computed by

the HS.

• Vertex Shader (VS)—Reads vertices, processes them. If the geometry

shader (GS) is active, the VS outputs its results to export shader-geometry

shader (ESGS) ring buffer. If the hull shader (HS) is active, the VS outputs

its results to the LDS. If neither the GS nor the HS is active, the VS outputs

its results to the parameter cache and position buffer. It does not introduce

new primitives. A vertex shader can invoke a Fetch Subroutine (FS), which

is a special global program for fetching vertex data that is treated, for

execution purposes, as part of the vertex program. The FS provides driver

independence between the process of fetching data required by a VS, and

the VS itself.

• Geometry Shader (GS)—Reads primitives from the VS ring buffer, and, for

each input primitive, writes zero or more primitives as output to the GS ring

buffer. This program type is optional; when active, it requires a DMA copy

(DC) program to be active. The GS simultaneously reads up to six vertices

from an off-chip memory buffer created by the VS; it outputs a variable

number of primitives to a second memory buffer.

• DMA Copy (DC)—Transfers data from the GS ring buffer into the parameter

cache and position buffer. It is required for systems running a geometry

shader.

AMD HD 6900 SERIES TECHNOLOGY

2-2 Program Types

• Pixel Shader (PS) or Fragment Shader—This type of program:

– receives pixel data from the rasterizer to be shaded,

– processes sets of pixel quads (four pixel-data elements arranged in a 2-

by-2 array (quad) in neighboring lanes of a compute unit), and

– writes output to up to eight local-memory buffers, called multiple render

targets (MRTs), each of which includes a frame buffer.

• Compute Shader (CS)—A generic program (compute kernel) that uses an

input work-item ID as an index to perform:

– gather reads on one or more sets of input data,

– arithmetic computation, and

– scatter writes to one or more set of output data to memory.

Compute shaders can write to multiple (up to eight) surfaces, which can be

a mix of multiple render targets (MRTs), unordered access views (UAVs), and

flat address space.

All program types accept the same instruction types, and all of the program types

can run on any of the available DPP-array pipelines that support these programs;

however, each kernel type has certain restrictions, which are described with that

type.

2.1.1 Data Flows

The host can initialize the HD 69XX GPU to run in multiple configurations. The

compute shader is independent of other shaders. Pipeline configurations depend

on whether tesselation is used and if the geometry shader is being used. Figure

1.2, on page 1-4 illustrates the processing order. Each type of flow is described

in the following subsections. Table 2.1 shows the legal combinations for HS, LS,

and DS.

Table 2.1 Data Flow When Different Shaders Stages are En/Disabled

VS HS DS GS Hardware Data Flow

on on on on Vertex block → tessellation block → GS block

LS → HS → TS → ES → GS → VS → PS

on on on off Vertex block → tesselation block →

LS → HS → TE → VS → PS

In case of streamout, tessellation engine (TE) must

expand the primitive to list the primitive type.

on off off on VS is treated as ES.

ES → GS → VS → PS

on off off off VS → PS

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