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AM335X CPU技术参考手册:TI公司详尽开发资源
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更新于2024-07-22
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"AM335X系列CPU是TI(德州仪器)公司生产的一款基于ARM Cortex-A8内核的微处理器,适用于嵌入式系统开发。该技术参考手册详细介绍了AM335X的特性和功能,包括不同硅片版本的功能差异和增强。"
AM335X ARM Cortex-A8 微处理器技术参考手册是一份关键的开发文档,它为开发者提供了深入理解AM335X系列芯片所需的信息。这个系列的CPU主要特点是集成了高性能的ARM Cortex-A8内核,这使得它们在处理复杂计算任务和运行操作系统时具有出色的能力。
1.1 AM335X系列
- 设备特性:AM335X家族的特性包括高效能、低功耗设计,适用于工业控制、嵌入式计算和消费电子等多种应用场景。
- 设备识别:通过设备ID可以准确识别出具体的AM335X型号,有助于开发者选择合适的硬件配置和软件兼容性。
- 功能识别:芯片的功能可以通过特定的标识来辨识,比如内存大小、外设接口等,这对于系统集成和应用开发至关重要。
1.2 硅片修订版功能差异和增强
随着产品的迭代更新,TI对AM335X进行了多次改进:
- RTC报警唤醒:增加了实时时钟(RTC)报警在深度睡眠模式下的唤醒功能,提高了节能效果。
- BOOTP标识变更:更新了BOOTP(Bootstrap Protocol)标识,以适应更灵活的网络启动配置。
- USB描述符产品字符串更改:修改了USB设备描述符中的产品字符串,以提供更准确的设备信息。
- DPLL电源开关控制和状态寄存器:添加了对数字锁相环(DPLL)电源的控制,增强了电源管理能力。
- CORE SRAM LDO保留模式控制:新增了对核心静态RAM低 dropout稳压器(LDO)保留模式的控制,优化了内存管理。
- GPMC_A9引脚复用选项:增加了GPMC_A9引脚的复用功能,便于实现RMI(远程内存接口)的引脚复用。
- nNMI输入信号极性改变:修改了外部中断nNMI(非中断请求)输入信号的极性,可能影响中断处理逻辑。
- vtp_ctrl寄存器中ncin和pcin位的默认值更改:这可能影响电压阈值编程的设置。
- RGMIIMode默认值改为无内部延迟:提升了以太网连接的性能。
- RMIIClock源的默认值更改:可能影响RMI(串行多媒体接口)的时钟配置。
- EMAC启动时确定操作速度的方法变化:改进了以太网MAC在启动时自适应速度检测的方式,确保了网络连接的稳定性。
- EFUSE_SMA寄存器的添加:用于帮助识别不同设备变体,方便了设备区分和故障排查。
AM335X系列微处理器具备丰富的功能和灵活性,并且随着硅片版本的更新,持续引入了新的特性和增强,为开发者提供了更多可能性。这份技术参考手册对于那些需要进行AM335X平台开发的工程师来说,是不可或缺的参考资料。
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List of Figures
3-1. Microprocessor Unit (MPU) Subsystem............................................................................... 165
3-2. Microprocessor Unit (MPU) Subsystem Signal Interface ........................................................... 167
3-3. MPU Subsystem Clocking Scheme ................................................................................... 168
3-4. Reset Scheme of the MPU Subsystem ............................................................................... 169
3-5. MPU Subsystem Power Domain Overview........................................................................... 172
5-1. SGX530 Integration...................................................................................................... 182
5-2. SGX Block Diagram ..................................................................................................... 184
6-1. Interrupt Controller Block Diagram .................................................................................... 187
6-2. IRQ/FIQ Processing Sequence ........................................................................................ 193
6-3. Nested IRQ/FIQ Processing Sequence .............................................................................. 197
6-4. INTC_REVISION Register .............................................................................................. 206
6-5. INTC_SYSCONFIG Register ........................................................................................... 207
6-6. INTC_SYSSTATUS Register........................................................................................... 208
6-7. INTC_SIR_IRQ Register ................................................................................................ 209
6-8. INTC_SIR_FIQ Register ................................................................................................ 210
6-9. INTC_CONTROL Register.............................................................................................. 211
6-10. INTC_PROTECTION Register ......................................................................................... 212
6-11. INTC_IDLE Register..................................................................................................... 213
6-12. INTC_IRQ_PRIORITY Register........................................................................................ 214
6-13. INTC_FIQ_PRIORITY Register ........................................................................................ 215
6-14. INTC_THRESHOLD Register .......................................................................................... 216
6-15. INTC_ITR0 Register ..................................................................................................... 217
6-16. INTC_MIR0 Register .................................................................................................... 218
6-17. INTC_MIR_CLEAR0 Register .......................................................................................... 219
6-18. INTC_MIR_SET0 Register.............................................................................................. 220
6-19. INTC_ISR_SET0 Register .............................................................................................. 221
6-20. INTC_ISR_CLEAR0 Register .......................................................................................... 222
6-21. INTC_PENDING_IRQ0 Register....................................................................................... 223
6-22. INTC_PENDING_FIQ0 Register ....................................................................................... 224
6-23. INTC_ITR1 Register ..................................................................................................... 225
6-24. INTC_MIR1 Register .................................................................................................... 226
6-25. INTC_MIR_CLEAR1 Register .......................................................................................... 227
6-26. INTC_MIR_SET1 Register.............................................................................................. 228
6-27. INTC_ISR_SET1 Register .............................................................................................. 229
6-28. INTC_ISR_CLEAR1 Register .......................................................................................... 230
6-29. INTC_PENDING_IRQ1 Register....................................................................................... 231
6-30. INTC_PENDING_FIQ1 Register ....................................................................................... 232
6-31. INTC_ITR2 Register ..................................................................................................... 233
6-32. INTC_MIR2 Register .................................................................................................... 234
6-33. INTC_MIR_CLEAR2 Register .......................................................................................... 235
6-34. INTC_MIR_SET2 Register.............................................................................................. 236
6-35. INTC_ISR_SET2 Register .............................................................................................. 237
6-36. INTC_ISR_CLEAR2 Register .......................................................................................... 238
6-37. INTC_PENDING_IRQ2 Register....................................................................................... 239
6-38. INTC_PENDING_FIQ2 Register ....................................................................................... 240
6-39. INTC_ITR3 Register ..................................................................................................... 241
6-40. INTC_MIR3 Register .................................................................................................... 242
16
List of Figures SPRUH73H–October 2011–Revised April 2013
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6-41. INTC_MIR_CLEAR3 Register .......................................................................................... 243
6-42. INTC_MIR_SET3 Register.............................................................................................. 244
6-43. INTC_ISR_SET3 Register .............................................................................................. 245
6-44. INTC_ISR_CLEAR3 Register .......................................................................................... 246
6-45. INTC_PENDING_IRQ3 Register....................................................................................... 247
6-46. INTC_PENDING_FIQ3 Register ....................................................................................... 248
6-47. INTC_ILR0 to INTC_ILR127 Register................................................................................. 249
7-1. GPMC Block Diagram ................................................................................................... 253
7-2. GPMC Integration........................................................................................................ 254
7-3. GPMC to 16-Bit Address/Data-Multiplexed Memory ................................................................ 258
7-4. GPMC to 16-Bit Non-multiplexed Memory............................................................................ 259
7-5. GPMC to 8-Bit NAND Device .......................................................................................... 259
7-6. Chip-Select Address Mapping and Decoding Mask ................................................................. 264
7-7. Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1) ...................... 267
7-8. Wait Behavior During a Synchronous Read Burst Access ......................................................... 269
7-9. Read to Read for an Address-Data Multiplexed Device, On Different CS, Without Bus Turnaround (CS0n
Attached to Fast Device)................................................................................................ 271
7-10. Read to Read / Write for an Address-Data Multiplexed Device, On Different CS, With Bus Turnaround.... 271
7-11. Read to Read / Write for a Address-Data or AAD-Multiplexed Device, On Same CS, With Bus
Turnaround................................................................................................................ 272
7-12. Asynchronous Single Read Operation on an Address/Data Multiplexed Device................................ 281
7-13. Two Asynchronous Single Read Accesses on an Address/Data Multiplexed Device (32-Bit Read Split
Into 2 × 16-Bit Read) .................................................................................................... 282
7-14. Asynchronous Single Write on an Address/Data-Multiplexed Device............................................. 283
7-15. Asynchronous Single-Read on an AAD-Multiplexed Device ....................................................... 284
7-16. Asynchronous Single Write on an AAD-Multiplexed Device ....................................................... 286
7-17. Synchronous Single Read (GPMCFCLKDIVIDER = 0) ............................................................. 288
7-18. Synchronous Single Read (GPMCFCLKDIVIDER = 1) ............................................................. 289
7-19. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0) .................................................. 291
7-20. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1) .................................................. 292
7-21. Synchronous Single Write on an Address/Data-Multiplexed Device .............................................. 293
7-22. Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode .................................. 294
7-23. Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode........................ 295
7-24. Asynchronous Single Read on an Address/Data-Nonmultiplexed Device ....................................... 297
7-25. Asynchronous Single Write on an Address/Data-Nonmultiplexed Device........................................ 298
7-26. Asynchronous Multiple (Page Mode) Read........................................................................... 299
7-27. NAND Command Latch Cycle.......................................................................................... 304
7-28. NAND Address Latch Cycle ............................................................................................ 305
7-29. NAND Data Read Cycle ................................................................................................ 306
7-30. NAND Data Write Cycle................................................................................................. 307
7-31. Hamming Code Accumulation Algorithm (1 of 2) .................................................................... 311
7-32. Hamming Code Accumulation Algorithm (2 of 2) .................................................................... 312
7-33. ECC Computation for a 256-Byte Data Stream (Read or Write) .................................................. 312
7-34. ECC Computation for a 512-Byte Data Stream (Read or Write) .................................................. 313
7-35. 128 Word16 ECC Computation ........................................................................................ 314
7-36. 256 Word16 ECC Computation ........................................................................................ 314
7-37. Manual Mode Sequence and Mapping................................................................................ 319
7-38. NAND Page Mapping and ECC: Per-Sector Schemes ............................................................. 324
7-39. NAND Page Mapping and ECC: Pooled Spare Schemes.......................................................... 325
7-40. NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC..................................... 326
17
SPRUH73H–October 2011–Revised April 2013 List of Figures
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7-41. NAND Read Cycle Optimization Timing Description ................................................................ 333
7-42. Programming Model Top-Level Diagram ............................................................................. 336
7-43. NOR Interfacing Timing Parameters Diagram ....................................................................... 343
7-44. NAND Command Latch Cycle Timing Simplified Example......................................................... 347
7-45. Synchronous NOR Single Read Simplified Example................................................................ 352
7-46. Asynchronous NOR Single Write Simplified Example .............................................................. 354
7-47. GPMC Connection to an External NOR Flash Memory............................................................. 356
7-48. Synchronous Burst Read Access (Timing Parameters in Clock Cycles) ......................................... 358
7-49. Asynchronous Single Read Access (Timing Parameters in Clock Cycles) ...................................... 360
7-50. Asynchronous Single Write Access (Timing Parameters in Clock Cycles)....................................... 362
7-51. GPMC_REVISION ....................................................................................................... 367
7-52. GPMC_SYSCONFIG .................................................................................................... 367
7-53. GPMC_SYSSTATUS.................................................................................................... 368
7-54. GPMC_IRQSTATUS .................................................................................................... 369
7-55. GPMC_IRQENABLE .................................................................................................... 370
7-56. GPMC_TIMEOUT_CONTROL ......................................................................................... 371
7-57. GPMC_ERR_ADDRESS................................................................................................ 371
7-58. GPMC_ERR_TYPE...................................................................................................... 372
7-59. GPMC_CONFIG ......................................................................................................... 373
7-60. GPMC_STATUS ......................................................................................................... 374
7-61. GPMC_CONFIG1_i...................................................................................................... 375
7-62. GPMC_CONFIG2_i...................................................................................................... 377
7-63. GPMC_CONFIG3_i...................................................................................................... 378
7-64. GPMC_CONFIG4_i...................................................................................................... 380
7-65. GPMC_CONFIG5_i...................................................................................................... 382
7-66. GPMC_CONFIG6_i...................................................................................................... 383
7-67. GPMC_CONFIG7_i...................................................................................................... 384
7-68. GPMC_NAND_COMMAND_i .......................................................................................... 385
7-69. GPMC_NAND_ADDRESS_i............................................................................................ 385
7-70. GPMC_NAND_DATA_i ................................................................................................. 385
7-71. GPMC_PREFETCH_CONFIG1........................................................................................ 386
7-72. GPMC_PREFETCH_CONFIG2........................................................................................ 388
7-73. GPMC_PREFETCH_CONTROL....................................................................................... 388
7-74. GPMC_PREFETCH_STATUS ......................................................................................... 389
7-75. GPMC_ECC_CONFIG .................................................................................................. 390
7-76. GPMC_ECC_CONTROL ............................................................................................... 391
7-77. GPMC_ECC_SIZE_CONFIG........................................................................................... 392
7-78. GPMC_ECCj_RESULT ................................................................................................. 394
7-79. GPMC_BCH_RESULT0_i .............................................................................................. 395
7-80. GPMC_BCH_RESULT1_i .............................................................................................. 395
7-81. GPMC_BCH_RESULT2_i .............................................................................................. 395
7-82. GPMC_BCH_RESULT3_i .............................................................................................. 396
7-83. GPMC_BCH_SWDATA ................................................................................................. 396
7-84. GPMC_BCH_RESULT4_i .............................................................................................. 396
7-85. GPMC_BCH_RESULT5_i .............................................................................................. 397
7-86. GPMC_BCH_RESULT6_i .............................................................................................. 397
7-87. OCMC RAM Integration................................................................................................. 399
7-88. DDR2/3/mDDR Memory Controller Signals .......................................................................... 404
7-89. DDR2/3/mDDR Subsystem Block Diagram .......................................................................... 406
18
List of Figures SPRUH73H–October 2011–Revised April 2013
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7-90. DDR2/3/mDDR Memory Controller FIFO Block Diagram........................................................... 407
7-91. EMIF_MOD_ID_REV Register ......................................................................................... 424
7-92. STATUS Register ........................................................................................................ 425
7-93. SDRAM_CONFIG Register ............................................................................................. 426
7-94. SDRAM_CONFIG_2 Register .......................................................................................... 428
7-95. SDRAM_REF_CTRL Register ......................................................................................... 429
7-96. SDRAM_REF_CTRL_SHDW Register................................................................................ 430
7-97. SDRAM_TIM_1 Register................................................................................................ 431
7-98. SDRAM_TIM_1_SHDW Register ...................................................................................... 432
7-99. SDRAM_TIM_2 Register................................................................................................ 433
7-100. SDRAM_TIM_2_SHDW Register ...................................................................................... 434
7-101. SDRAM_TIM_3 Register................................................................................................ 435
7-102. SDRAM_TIM_3_SHDW Register ...................................................................................... 436
7-103. PWR_MGMT_CTRL Register .......................................................................................... 437
7-104. PWR_MGMT_CTRL_SHDW Register ................................................................................ 439
7-105. Interface Configuration Register ....................................................................................... 440
7-106. Interface Configuration Value 1 Register ............................................................................. 441
7-107. Interface Configuration Value 2 Register ............................................................................. 442
7-108. PERF_CNT_1 Register ................................................................................................. 443
7-109. PERF_CNT_2 Register ................................................................................................. 444
7-110. PERF_CNT_CFG Register ............................................................................................. 445
7-111. PERF_CNT_SEL Register.............................................................................................. 446
7-112. PERF_CNT_TIM Register .............................................................................................. 447
7-113. READ_IDLE_CTRL Register ........................................................................................... 448
7-114. READ_IDLE_CTRL_SHDW Register ................................................................................. 449
7-115. IRQSTATUS_RAW_SYS Register .................................................................................... 450
7-116. IRQSTATUS_SYS Register ............................................................................................ 451
7-117. IRQENABLE_SET_SYS Register...................................................................................... 452
7-118. IRQENABLE_CLR_SYS Register ..................................................................................... 453
7-119. ZQ_CONFIG Register ................................................................................................... 454
7-120. Read-Write Leveling Ramp Window Register........................................................................ 455
7-121. Read-Write Leveling Ramp Control Register......................................................................... 456
7-122. Read-Write Leveling Control Register................................................................................. 457
7-123. DDR_PHY_CTRL_1 Register .......................................................................................... 458
7-124. DDR_PHY_CTRL_1_SHDW Register ................................................................................ 460
7-125. Priority to Class of Service Mapping Register........................................................................ 462
7-126. Connection ID to Class of Service 1 Mapping Register............................................................. 463
7-127. Connection ID to Class of Service 2 Mapping Register............................................................. 464
7-128. Read Write Execution Threshold Register............................................................................ 466
7-129. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0).................................................................. 469
7-130. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register(
CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) ........................................................................ 469
7-131. DDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0) ...................................................................... 470
7-132. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0)).............................................................. 470
7-133. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) ..................................................................... 471
7-134. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
19
SPRUH73H–October 2011–Revised April 2013 List of Figures
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(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0) .................................................................... 472
7-135. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0).................................................................... 472
7-136. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) ................................................................. 473
7-137. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio
Register(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0).................................................... 473
7-138. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0)............................................................. 474
7-139. DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS)...... 475
7-140. ELM Integration .......................................................................................................... 477
7-141. ELM Revision Register (ELM_REVISION) ........................................................................... 488
7-142. ELM System Configuration Register (ELM_SYSCONFIG)......................................................... 488
7-143. ELM System Status Register (ELM_SYSSTATUS) ................................................................. 489
7-144. ELM Interrupt Status Register (ELM_IRQSTATUS)................................................................. 490
7-145. ELM Interrupt Enable Register (ELM_IRQENABLE)................................................................ 492
7-146. ELM Location Configuration Register (ELM_LOCATION_CONFIG).............................................. 493
7-147. ELM Page Definition Register (ELM_PAGE_CTRL) ................................................................ 494
7-148. ELM_SYNDROME_FRAGMENT_0_i Register ...................................................................... 495
7-149. ELM_SYNDROME_FRAGMENT_1_i Register ...................................................................... 495
7-150. ELM_SYNDROME_FRAGMENT_2_i Register ...................................................................... 495
7-151. ELM_SYNDROME_FRAGMENT_3_i Register ...................................................................... 496
7-152. ELM_SYNDROME_FRAGMENT_4_i Register ...................................................................... 496
7-153. ELM_SYNDROME_FRAGMENT_5_i Register ...................................................................... 496
7-154. ELM_SYNDROME_FRAGMENT_6_i Register ...................................................................... 497
7-155. ELM_LOCATION_STATUS_i Register................................................................................ 497
7-156. ELM_ERROR_LOCATION_0-15_i Registers ........................................................................ 498
8-1. Functional and Interface Clocks ....................................................................................... 500
8-2. Generic Clock Domain .................................................................................................. 505
8-3. Clock Domain State Transitions ....................................................................................... 505
8-4. Generic Power Domain Architecture .................................................................................. 507
8-5. High Level System View for RTC-only Mode ........................................................................ 512
8-6. System Level View of Power Management of Cortex A8 MPU and Cortex M3 ................................. 515
8-7. IPC Mechanism .......................................................................................................... 516
8-8. ADPLLS ................................................................................................................... 520
8-9. Basic Structure of the ADPLLLJ ....................................................................................... 522
8-10. Core PLL .................................................................................................................. 525
8-11. Peripheral PLL Structure................................................................................................ 528
8-12. MPU Subsystem PLL Structure ........................................................................................ 530
8-13. Display PLL Structure ................................................................................................... 531
8-14. DDR PLL Structure ...................................................................................................... 532
8-15. CLKOUT Signals......................................................................................................... 533
8-16. Watchdog Timer Clock Selection ...................................................................................... 533
8-17. Timer Clock Selection ................................................................................................... 534
8-18. RTC, VTP, and Debounce Clock Selection .......................................................................... 535
8-19. PORz ...................................................................................................................... 537
8-20. External System Reset.................................................................................................. 538
8-21. Warm Reset Sequence (External Warm Reset Source)............................................................ 539
8-22. Warm Reset Sequence (Internal Warm Reset Source)............................................................. 540
8-23. CM_PER_L4LS_CLKSTCTRL Register .............................................................................. 550
20
List of Figures SPRUH73H–October 2011–Revised April 2013
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