没有合适的资源?快使用搜索试试~ 我知道了~
首页SystemVerilog IEEE 1800-2009:设计与验证构建标准详解
SystemVerilog IEEE 1800-2009:设计与验证构建标准详解
需积分: 14 8 下载量 8 浏览量
更新于2024-07-19
收藏 7.07MB PDF 举报
IEEE Std 1800-2009是针对硬件设计、规格说明和验证的统一语言SystemVerilog的IEEE标准。该标准是在IEEE Std 1364-2005(Verilog硬件描述语言)和IEEE Std 1800-2005合并的基础上形成的,旨在提供一个更全面和兼容的设计工具。标准的主要目标是为硬件工程师提供一套强大且灵活的工具,以便于描述、设计和验证数字系统。
标准的第1部分涵盖了设计和验证构建的基础,包括概述、标准范围、目的、两个标准的合并、特殊术语、标准中的约定、语法描述、颜色使用规范、标准内容、已废弃的条款以及示例和前置条件。这部分内容着重于介绍SystemVerilog的基本构造元素,如模块、程序、接口、检查器、原语、子例程、包、配置等。
第3部分详细讨论了设计和验证的基本组件,如设计元素、模块结构、程序执行、接口定义、编译和详述过程、名称空间管理、时间和精度控制等。此外,还介绍了模拟调度语义,包括事件模拟、分层事件调度算法、确定性和非确定性行为、同步与并发、以及编程接口控制点(PLI回调)。
4.1至4.10章节深入解析了硬件模型的执行和验证环境中的调度机制,包括执行顺序、事件驱动的模拟、模拟算法的参考、以及如何处理不确定性、竞态条件和赋值的调度影响。这些章节对于理解SystemVerilog在实际设计中的行为和性能至关重要。
该标准的制定者是IEEE计算机学会设计自动化标准委员会和IEEE标准协会企业顾问组,最终于2009年11月得到批准。通过整合Verilog和SystemVerilog的优点,IEEE Std 1800-2009为硬件设计者提供了一个强大的工具,支持从概念设计到实现和验证的全过程。理解和遵循这个标准,设计师可以确保他们的代码符合行业最佳实践,并且能够在多个层次上进行精确和高效的模拟与验证。
xiv Copyright ©2009 IEEE. All rights reserved.
20.7 Array querying functions ............................................................................................................. 524
20.8 Math functions ............................................................................................................................. 526
20.9 Severity tasks ............................................................................................................................... 528
20.10 Elaboration system tasks.............................................................................................................. 528
20.11 Assertion control system tasks..................................................................................................... 530
20.12 Assertion action control system tasks.......................................................................................... 531
20.13 Assertion system functions .......................................................................................................... 533
20.14 Coverage system functions .......................................................................................................... 534
20.15 Probabilistic distribution functions.............................................................................................. 534
20.16 Stochastic analysis tasks and functions ....................................................................................... 536
20.17 Programmable logic array (PLA) modeling system tasks ........................................................... 538
20.18 Miscellaneous tasks and functions............................................................................................... 542
21. I/O system tasks and system functions .................................................................................................. 543
21.1 General......................................................................................................................................... 543
21.2 Display system tasks.................................................................................................................... 543
21.3 File input-output system tasks and system functions................................................................... 554
21.4 Loading memory array data from a file .......................................................................................565
21.5 Writing memory array data to a file............................................................................................. 568
21.6 Command line input..................................................................................................................... 569
21.7 Value change dump (VCD) files ................................................................................................. 572
22. Compiler directives................................................................................................................................ 593
22.1 General......................................................................................................................................... 593
22.2 Overview ..................................................................................................................................... 593
22.3 `resetall......................................................................................................................................... 593
22.4 `include ........................................................................................................................................ 594
22.5 `define, `undef and `undefineall .................................................................................................. 594
22.6 `ifdef, `else, `elsif, `endif, `ifndef ................................................................................................ 600
22.7 `timescale ..................................................................................................................................... 603
22.8 `default_nettype ........................................................................................................................... 604
22.9 `unconnected_drive and `nounconnected_drive .......................................................................... 605
22.10 `celldefine and `endcelldefine...................................................................................................... 605
22.11 `pragma ........................................................................................................................................ 605
22.12 `line .............................................................................................................................................. 606
22.13 `__FILE__ and `__LINE__ ......................................................................................................... 607
22.14 `begin_keywords, `end_keywords ............................................................................................... 608
Part Two:
Hierarchy Constructs
23. Modules and hierarchy........................................................................................................................... 614
23.1 General......................................................................................................................................... 614
23.2 Module definitions....................................................................................................................... 614
23.3 Module instances (hierarchy)....................................................................................................... 626
23.4 Nested modules............................................................................................................................ 636
23.5 Extern modules ............................................................................................................................ 637
23.6 Hierarchical names ...................................................................................................................... 638
23.7 Member selects and hierarchical names ...................................................................................... 641
23.8 Upwards name referencing .......................................................................................................... 642
23.9 Scope rules .................................................................................................................................. 644
23.10 Overriding module parameters .................................................................................................... 646
23.11 Binding auxiliary code to scopes or instances............................................................................. 654
24. Programs ................................................................................................................................................ 659
24.1 General......................................................................................................................................... 659
24.2 Overview...................................................................................................................................... 659
Copyright ©2009 IEEE. All rights reserved. xv
24.3 The program construct ................................................................................................................. 659
24.4 Eliminating testbench races ......................................................................................................... 663
24.5 Blocking tasks in cycle/event mode............................................................................................. 663
24.6 Programwide space and anonymous programs............................................................................ 664
24.7 Program control tasks .................................................................................................................. 664
25. Interfaces................................................................................................................................................ 665
25.1 General......................................................................................................................................... 665
25.2 Overview...................................................................................................................................... 665
25.3 Interface syntax............................................................................................................................ 666
25.4 Ports in interfaces......................................................................................................................... 670
25.5 Modports ...................................................................................................................................... 671
25.6 Interfaces and specify blocks....................................................................................................... 677
25.7 Tasks and functions in interfaces................................................................................................. 678
25.8 Parameterized interfaces .............................................................................................................. 684
25.9 Virtual interfaces.......................................................................................................................... 686
25.10
Access to interface objects
........................................................................................................... 691
26. Packages................................................................................................................................................. 693
26.1 General......................................................................................................................................... 693
26.2 Package declarations.................................................................................................................... 693
26.3 Referencing data in packages ...................................................................................................... 694
26.4 Using packages in module headers.............................................................................................. 698
26.5 Search order rules ........................................................................................................................ 699
26.6 Exporting imported names from packages .................................................................................. 701
26.7 The std built-in package............................................................................................................... 702
27. Generate constructs................................................................................................................................ 705
27.1 General......................................................................................................................................... 705
27.2 Overview...................................................................................................................................... 705
27.3 Generate construct syntax............................................................................................................ 705
27.4 Loop generate constructs ............................................................................................................. 707
27.5 Conditional generate constructs................................................................................................... 711
27.6 External names for unnamed generate blocks ............................................................................. 714
28. Gate-level and switch-level modeling ................................................................................................... 717
28.1 General......................................................................................................................................... 717
28.2 Overview...................................................................................................................................... 717
28.3 Gate and switch declaration syntax ............................................................................................. 717
28.4 and, nand, nor, or, xor, and xnor gates......................................................................................... 723
28.5 buf and not gates .......................................................................................................................... 724
28.6 bufif1, bufif0, notif1, and notif0 gates......................................................................................... 725
28.7 MOS switches .............................................................................................................................. 726
28.8 Bidirectional pass switches.......................................................................................................... 727
28.9 CMOS switches ........................................................................................................................... 728
28.10 pullup and pulldown sources ....................................................................................................... 729
28.11 Logic strength modeling .............................................................................................................. 729
28.12 Strengths and values of combined signals ...................................................................................731
28.13 Strength reduction by nonresistive devices .................................................................................744
28.14 Strength reduction by resistive devices ....................................................................................... 744
28.15 Strengths of net types................................................................................................................... 744
28.16 Gate and net delays ...................................................................................................................... 745
29. User defined primitives (UDPs) ............................................................................................................ 749
29.1 General......................................................................................................................................... 749
29.2 Overview...................................................................................................................................... 749
29.3 UDP definition............................................................................................................................. 749
29.4 Combinational UDPs ................................................................................................................... 753
xvi Copyright ©2009 IEEE. All rights reserved.
29.5 Level-sensitive sequential UDPs ................................................................................................. 754
29.6 Edge-sensitive sequential UDPs .................................................................................................. 754
29.7 Sequential UDP initialization ...................................................................................................... 755
29.8 UDP instances.............................................................................................................................. 757
29.9 Mixing level-sensitive and edge-sensitive descriptions............................................................... 758
29.10 Level-sensitive dominance .......................................................................................................... 759
30. Specify blocks........................................................................................................................................ 761
30.1 General......................................................................................................................................... 761
30.2 Overview...................................................................................................................................... 761
30.3 Specify block declaration............................................................................................................. 761
30.4 Module path declarations............................................................................................................. 762
30.5 Assigning delays to module paths ............................................................................................... 771
30.6 Mixing module path delays and distributed delays ..................................................................... 775
30.7 Detailed control of pulse filtering behavior................................................................................. 776
31. Timing checks........................................................................................................................................ 785
31.1 General......................................................................................................................................... 785
31.2 Overview...................................................................................................................................... 785
31.3 Timing checks using a stability window......................................................................................788
31.4 Timing checks for clock and control signals ............................................................................... 795
31.5 Edge-control specifiers ................................................................................................................ 804
31.6 Notifiers: user-defined responses to timing violations ................................................................ 805
31.7 Enabling timing checks with conditioned events ........................................................................ 807
31.8 Vector signals in timing checks ................................................................................................... 808
31.9 Negative timing checks................................................................................................................ 809
32. Backannotation using the standard delay format (SDF) ........................................................................ 815
32.1 General......................................................................................................................................... 815
32.2 Overview...................................................................................................................................... 815
32.3 The SDF annotator....................................................................................................................... 815
32.4 Mapping of SDF constructs to SystemVerilog ............................................................................ 815
32.5 Multiple annotations .................................................................................................................... 820
32.6 Multiple SDF files ....................................................................................................................... 821
32.7 Pulse limit annotation .................................................................................................................. 821
32.8 SDF to SystemVerilog delay value mapping............................................................................... 822
32.9 Loading timing data from an SDF file......................................................................................... 822
33. Configuring the contents of a design ..................................................................................................... 825
33.1 General......................................................................................................................................... 825
33.2 Overview...................................................................................................................................... 825
33.3 Libraries ....................................................................................................................................... 826
33.4 Configurations .............................................................................................................
................ 828
33.5
Using libraries and configs .
......................................................................................................... 834
33.6 Configuration examples............................................................................................................... 835
33.7 Displaying library binding information ....................................................................................... 837
33.8 Library mapping examples .......................................................................................................... 837
34. Protected envelopes ............................................................................................................................... 841
34.1 General......................................................................................................................................... 841
34.2 Overview...................................................................................................................................... 841
34.3 Processing protected envelopes ................................................................................................... 841
34.4 Protect pragma directives............................................................................................................. 843
34.5 Protect pragma keywords............................................................................................................. 845
Copyright ©2009 IEEE. All rights reserved. xvii
Part Three:
Application Programming Interfaces
35. Direct programming interface (DPI)...................................................................................................... 862
35.1 General......................................................................................................................................... 862
35.2 Overview...................................................................................................................................... 862
35.3 Two layers of the DPI .................................................................................................................. 863
35.4 Global name space of imported and exported functions.............................................................. 864
35.5 Imported tasks and functions ....................................................................................................... 865
35.6 Calling imported functions .......................................................................................................... 872
35.7 Exported functions....................................................................................................................... 874
35.8 Exported tasks.............................................................................................................................. 875
35.9 Disabling DPI tasks and functions............................................................................................... 875
36. Programming language interface (PLI/VPI) overview.......................................................................... 877
36.1 General......................................................................................................................................... 877
36.2 PLI purpose and history............................................................................................................... 877
36.3 User-defined system task and system function names................................................................. 878
36.4 User-defined system task and system function arguments .......................................................... 879
36.5 User-defined system task and system function types .................................................................. 879
36.6 User-supplied PLI applications.................................................................................................... 879
36.7 PLI include files........................................................................................................................... 879
36.8 VPI sizetf, compiletf and calltf routines ...................................................................................... 879
36.9 PLI mechanism ............................................................................................................................ 880
36.10 VPI access to SystemVerilog objects and simulation objects ..................................................... 882
36.11 List of VPI routines by functional category................................................................................. 883
36.12 VPI backwards compatibility features and limitations ................................................................ 885
37. VPI object model diagrams.................................................................................................................... 891
37.1 General......................................................................................................................................... 891
37.2 VPI Handles................................................................................................................................. 891
37.3 VPI object classifications............................................................................................................. 892
37.4 Key to data model diagrams ........................................................................................................ 898
37.5 Module ....................................................................................................................................... 901
37.6 Interface .................................................................................................................................... 902
37.7 Modport ...................................................................................................................................... 902
37.8 Interface task or function declaration ....................................................................................
..... 902
37.9
Program ...
.................................................................................................................................. 903
37.10 Instance ....................................................................................................................................... 904
37.11 Instance arrays ............................................................................................................................ 906
37.12 Scope ........................................................................................................................................... 907
37.13 IO declaration ............................................................................................................................. 908
37.14 Ports ............................................................................................................................................ 909
37.15 Reference objects ........................................................................................................................ 910
37.16 Nets .............................................................................................................................................. 913
37.17 Variables ..................................................................................................................................... 917
37.18 Packed array variables ................................................................................................................ 920
37.19 Variable select ............................................................................................................................. 921
37.20 Memory........................................................................................................................................ 922
37.21 Variable drivers and loads .......................................................................................................... 922
37.22 Object Range................................................................................................................................ 923
37.23 Typespec ..................................................................................................................................... 924
37.24 Structures and unions................................................................................................................... 926
37.25 Named events .............................................................................................................................. 927
37.26 Parameter, spec param, def param, param assign ...................................................................... 928
37.27 Class definition ........................................................................................................................... 929
xviii Copyright ©2009 IEEE. All rights reserved.
37.28 Class typespec ............................................................................................................................. 930
37.29 Class variables and class objects ................................................................................................. 932
37.30 Constraint, constraint ordering, distribution ............................................................................... 934
37.31 Primitive, prim term..................................................................................................................... 935
37.32 UDP ............................................................................................................................................. 936
37.33 Intermodule path .......................................................................................................................... 936
37.34 Constraint expression .................................................................................................................. 937
37.35 Module path, path term ............................................................................................................... 937
37.36 Timing check ............................................................................................................................... 938
37.37 Task and function declaration ..................................................................................................... 939
37.38 Task and function call ................................................................................................................. 940
37.39 Frames ......................................................................................................................................... 942
37.40 Threads ........................................................................................................................................ 943
37.41 Delay terminals ............................................................................................................................ 943
37.42 Net drivers and loads ................................................................................................................... 944
37.43 Continuous assignment ................................................................................................................ 945
37.44 Clocking block ............................................................................................................................ 946
37.45 Assertion ..................................................................................................................................... 947
37.46 Concurrent assertions ................................................................................................................ 948
37.47 Property declaration .................................................................................................................... 949
37.48 Property specification ............................................................................................................... 950
37.49 Sequence declaration .................................................................................................................. 951
37.50 Sequence expression ................................................................................................................... 952
37.51 Immediate assertions ................................................................................................................... 953
37.52 Multiclock sequence expression ............................................................................................... 954
37.53 Let ............................................................................................................................................ 954
37.54 Simple expressions ..................................................................................................................... 955
37.55 Expressions ............................................................................................................................... 956
37.56 Atomic statement ........................................................................................................................ 959
37.57 Event statement ........................................................................................................................... 960
37.58 Process ........................................................................................................................................ 960
37.59 Assignment ................................................................................................................................. 961
37.60 Event control ............................................................................................................................... 961
37.61 While, repeat................................................................................................................................ 962
37.62 Waits ........................................................................................................................................... 962
37.63 Delay control................................................................................................................................ 962
37.64 Repeat control .............................................................................................................................. 963
37.65 Forever ......................................................................................................................................... 963
37.66 If, if–else ...................................................................................................................................... 963
37.67 Case, pattern ............................................................................................................
.................... 964
37.68
Expect .
........................................................................................................................................ 965
37.69 For ............................................................................................................................................... 965
37.70 Do-while, foreach ........................................................................................................................ 965
37.71 Alias statement ............................................................................................................................ 966
37.72 Disables........................................................................................................................................ 967
37.73 Return statement ......................................................................................................................... 967
37.74 Assign statement, deassign, force, release................................................................................... 967
37.75 Callback ....................................................................................................................................... 968
37.76 Time queue .................................................................................................................................. 968
37.77 Active time format ....................................................................................................................... 969
37.78 Attribute ...................................................................................................................................... 970
37.79 Iterator.......................................................................................................................................... 971
37.80 Generates .................................................................................................................................... 972
38. VPI routine definitions........................................................................................................................... 975
剩余1284页未读,继续阅读
2018-02-26 上传
2020-05-04 上传
2020-10-15 上传
2021-10-01 上传
2011-04-12 上传
2020-09-20 上传
2022-07-13 上传
2020-03-11 上传
2021-10-04 上传
luoyanghero
- 粉丝: 5
- 资源: 31
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- C++ Qt影院票务系统源码发布,代码稳定,高分毕业设计首选
- 纯CSS3实现逼真火焰手提灯动画效果
- Java编程基础课后练习答案解析
- typescript-atomizer: Atom 插件实现 TypeScript 语言与工具支持
- 51单片机项目源码分享:课程设计与毕设实践
- Qt画图程序实战:多文档与单文档示例解析
- 全屏H5圆圈缩放矩阵动画背景特效实现
- C#实现的手机触摸板服务端应用
- 数据结构与算法学习资源压缩包介绍
- stream-notifier: 简化Node.js流错误与成功通知方案
- 网页表格选择导出Excel的jQuery实例教程
- Prj19购物车系统项目压缩包解析
- 数据结构与算法学习实践指南
- Qt5实现A*寻路算法:结合C++和GUI
- terser-brunch:现代JavaScript文件压缩工具
- 掌握Power BI导出明细数据的操作指南
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功