Xtensa ISA Reference Manual for Operating System Development

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"Tensilica的ISA开发手册，专注于操作系统开发" Tensilica的Xtensa Instruction Set Architecture (ISA) 是一种高度可配置和可扩展的微处理器架构，广泛用于设计高性能、低功耗的嵌入式处理器。Xtensa ISA 提供了丰富的指令集选项，使得开发者可以根据具体应用的需求定制处理器核心，从而优化性能和能效。这份参考手册是针对所有Xtensa处理器内核的详细指南，涵盖了从基础指令到高级功能的所有方面。手册的核心内容可能包括以下几个部分： 1. **指令集概述**：介绍Xtensa ISA的基本结构和设计原则，以及它与传统RISC（精简指令集计算）和CISC（复杂指令集计算）的区别。它可能会详细阐述ISA的可配置性，例如，开发者可以选择是否包含浮点运算单元、向量处理单元或其他特定功能。 2. **指令集详细说明**：列出Xtensa ISA中的所有指令，包括它们的操作、编码格式、参数和使用场景。这通常会涉及数据处理、控制流、内存访问和I/O操作等基本指令，以及针对特定应用的扩展指令。 3. **寻址模式**：详细解释Xtensa处理器支持的各种寻址方式，这些寻址模式可以提供灵活性，支持高效的数据访问和处理。 4. **寄存器组织**：描述处理器的寄存器布局，包括通用寄存器、浮点寄存器、控制寄存器等，以及它们在编程时如何使用。 5. **处理器核心配置**：说明如何根据需求定制处理器核心，包括选择不同的流水线深度、指令预取策略、中断处理机制等。 6. **操作系统支持**：由于描述适合操作系统开发，手册可能会涵盖与OS相关的特性，如异常处理、中断服务例程、多任务环境下的上下文切换等。 7. **开发工具和软件支持**：介绍用于开发和调试Xtensa处理器应用的工具链，如编译器、模拟器、调试器等，并可能提供关于如何使用这些工具的指导。 8. **性能优化**：提供指导，帮助开发者利用Xtensa ISA的特性进行代码优化，以实现最佳性能。 9. **知识产权保护和法律条款**：Tensilica明确指出，此文档提供的信息仅用于系统和软件开发，不包含任何专利、版权或其他知识产权的明示或暗示授权。这份Xtensa ISA参考手册是开发者深入理解和利用Tensilica处理器技术的关键资源，对于设计高效、定制化操作系统以及相关的硬件和软件平台具有极高的价值。

List of Tables

xvi Xtensa Instruction Set Architecture (ISA) Reference Manual

Table 5–143. BR - Special Register #4 ...........................................................................223

Table 5–144. LITBASE - Special Register #5..................................................................224

Table 5–145. SCOMPARE1 - Special Register #12............................................................224

Table 5–146. PREFCTL - Special Register #40................................................................224

Table 5–147. PS - Special Register #230........................................................................225

Table 5–148. PS.INTLEVEL - Special Register #230 (part)..............................................226

Table 5–149. PS.EXCM - Special Register #230 (part) .....................................................227

Table 5–150. PS.UM - Special Register #230 (part) .........................................................228

Table 5–151. PS.RING - Special Register #230 (part) .....................................................228

Table 5–152. PS.OWB - Special Register #230 (part) .......................................................229

Table 5–153. PS.CALLINC - Special Register #230 (part)................................................229

Table 5–154. PS.WOE - Special Register #230 (part) .......................................................229

Table 5–155. WindowBase - Special Register #72..........................................................230

Table 5–156. WindowStart - Special Register #73 ........................................................230

Table 5–157. PTEVADDR - Special Register #83..............................................................231

Table 5–158. RASID - Special Register #90....................................................................231

Table 5–159. ITLBCFG - Special Register #91................................................................232

Table 5–160. DTLBCFG - Special Register #92................................................................232

Table 5–161. EXCCAUSE - Special Register #232 ............................................................233

Table 5–162. EXCVADDR - Special Register #238 ............................................................233

Table 5–163. VECBASE - Special Register #231 ..............................................................233

Table 5–164. MESR - Special Register #109....................................................................234

Table 5–165. MECR - Special Register #110 ....................................................................234

Table 5–166. MEVADDR - Special Register #111 ..............................................................234

Table 5–167. DEBUGCAUSE - Special Register #233 ........................................................235

Table 5–168. EPC1 - Special Register #177....................................................................235

Table 5–169. EPC2..7 - Special Register #178-183........................................................235

Table 5–170. DEPC - Special Register #192....................................................................236

Table 5–171. MEPC - Special Register #106....................................................................236

Table 5–172. EPS2..7 - Special Register #194-199........................................................236

Table 5–173. MEPS - Special Register #107....................................................................237

Table 5–174. EXCSAVE1 - Special Register #192 ............................................................237

Table 5–175. EXCSAVE2..7- Special Register #210-215..................................................237

Table 5–176. MESAVE- Special Register #108..................................................................238

Table 5–177. INTERRUPT - Special Register #226 (read).................................................238

Table 5–178. INTSET - Special Register #226 (write) ......................................................239

Table 5–179. INTCLEAR - Special Register #227 ............................................................239

Table 5–180. INTENABLE - Special Register #228 ..........................................................240

Table 5–181. ICOUNT - Special Register #236................................................................240

Table 5–182. ICOUNTLEVEL - Special Register #237 ......................................................241

Table 5–183. CCOUNT - Special Register #234................................................................241

Table 5–184. CCOMPARE0..2 - Special Register #240-242..............................................242

Table 5–185. IBREAKENABLE - Special Register #96 ......................................................242

Table 5–186. IBREAKA0..1 - Special Register #128-129................................................243

Table 5–187. DBREAKC0..1 - Special Register #160-161................................................243

Table 5–188. DBREAKA0..1 - Special Register #144-145................................................244

Table 5–189. PRID - Special Register #235....................................................................244

Table 5–190. MMID - Special Register #89......................................................................244

Table 5–191. DDR - Special Register #104......................................................................245

List of Tables

Xtensa Instruction Set Architecture (ISA) Reference Manual xvii

Table 5–192. CPENABLE - Special Register #224 ............................................................245

Table 5–193. MISC0..3 - Special Register #244-247......................................................245

Table 5–194. ATOMCTL - Special Register #99................................................................246

Table 5–195. Numerical List of User Registers...................................................................246

Table 5–196. THREADPTR - User Register #231..............................................................247

Table 5–197. FCR - User Register #232 .........................................................................248

Table 5–198. FSR - User Register #233 .........................................................................248

Table 6–199. Performance of L32R Instruction ..................................................................393

Table 7–200. Uses Of Instruction Fields............................................................................583

Table 7–201. Whole Opcode Space..................................................................................585

Table 7–202. QRST (from Table 7–201) Formats RRR, CALLX, and RSR (t, s, r, op2 vary) ....585

Table 7–203. RST0 (from Table 7–202) Formats RRR and CALLX (t, s, r vary) .....................586

Table 7–204. ST0 (from Table 7–203 Formats RRR and CALLX (t, s vary)............................586

Table 7–205. SNM0 (from Table 7–204) Format CALLX (n, s vary) ......................................586

Table 7–206. JR (from Table 7–205) Format CALLX (s varies) ............................................586

Table 7–207. CALLX (from Table 7–205) Format CALLX (s varies) ......................................586

Table 7–208. SYNC (from Table 7–204) Format RRR (s varies)...........................................586

Table 7–209. RFEI (from Table 7–204) Format RRR (s varies) ............................................587

Table 7–210. RFET (from Table 7–209) Format RRR (no bits vary)......................................587

Table 7–211. ST1 (from Table 7–203) Format RRR (t, s vary) .............................................587

Table 7–212. TLB (from Table 7–203) Format RRR (t, s vary) .............................................587

Table 7–213. RT0 (from Table 7–203) Format RRR (t, r vary)..............................................588

Table 7–214. RST1 (from Table 7–202) Format RRR (t, s, r vary) ........................................588

Table 7–215. ACCER (from Table 7–214) Format RRR (t, s vary) ........................................588

Table 7–216. IMP (from Table 7–214) Format RRR (t, s vary) (Section 7.3.3)........................588

Table 7–217. RFDX (from Table 7–216) Format RRR (s varies)...........................................589

Table 7–218. RST2 (from Table 7–202) Format RRR (t, s, r vary) ........................................589

Table 7–219. RST3 (from Table 7–202) Formats RRR and RSR (t, s, r vary).........................589

Table 7–220. LSCX (from Table 7–202) Format RRR (t, s, r vary) ........................................589

Table 7–221. LSC4 (from Table 7–202) Format RRI4 (t, s, r vary) ........................................590

Table 7–222. FP0 (from Table 7–202) Format RRR (t, s, r vary)...........................................590

Table 7–223. FP1OP (from Table 7–222) Format RRR (s, r vary).........................................590

Table 7–224. FP1 (from Table 7–202) Format RRR (t, s, r vary)...........................................590

Table 7–225. LSAI (from Table 7–201) Formats RRI8 and RRI4 (t, s, imm8 vary) ..................591

Table 7–226. CACHE (from Table 7–225) Formats RRI8 and RRI4 (s, imm8 vary).................591

Table 7–227. DCE (from Table 7–226) Format RRI4 (s, imm4 vary) .....................................591

Table 7–228. ICE (from Table 7–226) Format RRI4 (s, imm4 vary).......................................591

Table 7–229. LSCI (from Table 7–201) Format RRI8 (t, s, imm8 vary) ..................................592

Table 7–230. MAC16 (from Table 7–201) Format RRR (t, s, r, op1 vary)...............................592

Table 7–231. MACID (from Table 7–230) Format RRR (t, s, r vary) ......................................592

Table 7–232. MACIA (from Table 7–230) Format RRR (t, s, r vary) ......................................592

Table 7–233. MACDD (from Table 7–230) Format RRR (t, s, r vary).....................................593

Table 7–234. MACAD (from Table 7–230) Format RRR (t, s, r vary).....................................593

Table 7–235. MACCD (from Table 7–230) Format RRR (t, s, r vary).....................................593

Table 7–236. MACCA (from Table 7–230) Format RRR (t, s, r vary).....................................593

Table 7–237. MACDA (from Table 7–230) Format RRR (t, s, r vary).....................................594

Table 7–238. MACAA (from Table 7–230) Format RRR (t, s, r vary) .....................................594

Table 7–239. MACI (from Table 7–230) Format RRR (t, s, r vary) ........................................594

Table 7–240. MACC (from Table 7–230) Format RRR (t, s, r vary) .......................................594

List of Tables

xviii Xtensa Instruction Set Architecture (ISA) Reference Manual

Table 7–241. CALLN (from Table 7–201) Format CALL (offset varies)..................................594

Table 7–242. SI (from Table 7–201) Formats CALL, BRI8 and BRI12(offset varies) ...............595

Table 7–243. BZ (from Table 7–242) Format BRI12 (s, imm12 vary) ....................................595

Table 7–244. BI0 (from Table 7–242) Format BRI8 (s, r, imm8 vary).....................................595

Table 7–245. BI1 (from Table 7–242) Formats BRI8 and BRI12 (s, r, imm8 vary)...................595

Table 7–246. B1 (from Table 7–245) Format BRI8 (s, imm8 vary) ........................................595

Table 7–247. B (from Table 7–201) Format RRI8 (t, s, imm8 vary) .......................................595

Table 7–248. ST2 (from Table 7–201) Formats RI7 and RI6 (s, r vary) .................................596

Table 7–249. ST3 (from Table 7–201) Format RRRN (t, s vary) ...........................................596

Table 7–250. S3 (from Table 7–249) Format RRRN (no fields vary) .....................................596

Table 8–251. Windowed AR Register Usage .....................................................................597

Table 8–252. CALL0 AR Register Usage ..........................................................................600

Table 8–253. Data Types and Alignment ...........................................................................600

Table 8–254. BR Register Usage .....................................................................................605

Table 8–255. Breakpoint Instruction Operand Conventions ................................................. 611

Table 8–256. Instruction Idioms........................................................................................614

Table 8–257. Xtensa Pipeline ..........................................................................................623

Table 9-258. Instructions Added ......................................................................................625

Table 9-259. Cache Attribute Register..............................................................................631

Table 9-260. Cache Attribute Special Register ..................................................................631

Table 9–261. T1050 Additional SYNC Requirements..........................................................635

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