ADRV9009：高性能双RF收发器解决方案

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"ADRV9009是一款高度集成的射频（RF）敏捷收发器，提供双发射器和接收器、集成的合成器以及数字信号处理功能。该集成电路为3G、4G和5G宏小区时分双工（TDD）基站应用提供了高性能和低功耗的灵活组合。" 在ADRV9009芯片中，其核心特性包括： 1. **双RF发射器和接收器**：这款芯片内置两个独立的发射和接收通道，可以同时处理两个不同的无线信号，这对于需要处理多个连接或频段的基站应用至关重要。 2. **集成的合成器**：ADRV9009集成了分数-N RF合成器，允许灵活地调整发射和接收频率，支持宽范围的频谱覆盖，这对于适应不同的通信标准和频率规划非常重要。 3. **观察接收器**：芯片还包含一个双输入共享观察接收器，可以监测和分析射频信号的质量，对于故障检测和系统优化具有重要意义。 4. **最大接收带宽200MHz**：这意味着ADRV9009能处理高达200MHz的接收信号速率，满足高速数据传输的需求。 5. **最大可调发射合成带宽450MHz**：这使得ADRV9009能够快速切换不同频段，适应动态频谱分配，适合多频段操作。 6. **最大观察接收器带宽450MHz**：与发射带宽相匹配，观察接收器的宽带能力有助于进行精确的信号分析和故障排查。 7. **完全集成的分数-N RF合成器和时钟合成器**：这些集成组件减少了外部组件的需求，简化了设计，并提高了系统的可靠性。 8. **多芯片相位同步**：RF本地振荡器（LO）和基带时钟之间的多芯片相位同步确保了信号的精确对齐，从而提高链路性能。 9. **符合JESD204B标准**：这表明ADRV9009遵循了高速串行接口标准，确保了与数字信号处理器（DSP）和其他数字接口的高效连接。在实际应用中，ADRV9009适用于基站建设，尤其是大型3G、4G和5G网络中的TDD基站，能够实现高效能、低能耗的无线通信。其广泛的调谐范围和高带宽能力使其成为满足现代通信需求的理想解决方案。同时，集成的信号处理功能和相位同步技术进一步降低了系统复杂性和成本，提高了整体系统的稳定性和性能。对于设计工程师来说，ADRV9009提供的详细文档将帮助他们理解和充分利用这款芯片的潜力，以构建高效、可靠的无线通信基础设施。

ADRV9009 Data Sheet

Rev. A | Page 16 of 128

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1 2 3 4 5 6 7 8 9 10 11 12 13 14

VSSA ORX2_IN+ ORX2_IN– VSSA RX2_IN+ RX2_IN– VSSA VSSA RX1_IN+ RX1_IN– VSSA ORX1_IN+ ORX1_IN– VSSA

VDDA1P3_

RX_RF

VSSA VSSA VSSA VSSA VSSA

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

VSSA VSSA VSSA VSSA VSSA VSSA

GPIO_3P3_0 GPIO_3P3_3

VDDA1P3_

RX_TX

VSSA

VDDA1P3_

RF_VCO_LDO

VDDA1P3_

RF_VCO_LDO

VDDA1P1_

RF_VCO

VDDA1P3_

RF_LO

VSSA

VDDA1P3_

AUX_VCO_

LDO

VSSA VDDA_3P3 GPIO_3P3_9 RBIAS

GPIO_3P3_1 GPIO_3P3_4 VSSA VSSA VSSA VSSA VSSA VSSA VSSA

VDDA1P1_

AUX_VCO

VSSA VSSA GPIO_3P3_8 GPIO_3P3_10

GPIO_3P3_2 GPIO_3P3_5 GPIO_3P3_6 VDDA1P8_BB VDDA1P3_BB VSSA REF_CLK_IN+ REF_CLK_IN– VSSA

AUX_SYNTH_

OUT

AUXADC_3 VDDA1P8_TX GPIO_3P3_7 GPIO_3P3_11

VSSA VSSA AUXADC_0 AUXADC_1 VSSA VSSA VSSA VSSA VSSA VSSA AUXADC_2 VSSA VSSA VSSA

VSSA VSSA VSSA VSSA

VDDA1P3_

CLOCK_ SYNTH

VSSA

VDDA1P3_

RF_SYNTH

VDDA1P3_

AUX_SYNTH

RF_SYNTH_

VTUNE

VSSA VSSA VSSA VSSA VSSA

TX2_OUT– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA TX1_OUT+

TX2_OUT+ VSSA GPIO_18 RESET

GP_

INTERRUPT

TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA TX1_OUT–

VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CS GPIO_14 GPIO_9 VSSA VSSA

VSSA VSSA SYNCIN1– SYNCIN1+ GPIO_6 GPIO_7 VSSD

VDDD1P3_

DIG

VDDD1P3_

DIG

VSSD GPIO_15 GPIO_8 SYNCOUT1– SYNCOUT1+

VDDA1P1_

CLOCK_VCO

VSSA SYNCIN0– SYNCIN0+ RX1_ENABLE TX1_ENABLE RX2_ENABLE TX2_ENABLE VSSA GPIO_17 GPIO_16

VDD_

INTERFACE

SYNCOUT0– SYNCOUT0+

VDDA1P3_

CLOCK_

VCO_LDO

VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA

VDDA1P3_

SER

VDDA1P3_

DES

SERDIN1– SERDIN1+ SERDIN0– SERDIN0+ VSSA

AUX_SYNTH_

VTUNE

VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+

VDDA1P3_

SER

VDDA1P3_

DES

VSSA SERDIN3– SERDIN3+ SERDIN2– SERDIN2+

ADRV9009

16499-900

Figure 6. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Type Mnemonic Description

A1, A4, A7, A8, A11, A14, B2 to

B6, B9 to B14, C4, C9, C11,

D3 to D9, D11, D12, E6, E9,

F1, F2, F5 to F10, F12 to

F14, G1 to G4, G6, G10 to

G14, H2 to H10, H13, J2,

J13, K1, K2, K13, K14, L1, L2,

M2, M9, N2, N7, N14, P2,

P3, P10

Input VSSA Analog Supply Voltage (V

A2, A3 Input ORX2_IN+, ORX2_IN− Differential Input for Observation Receiver 2. When unused, connect

these pins to ground.

A5, A6 Input RX2_IN+, RX2_IN− Differential Input for Main Receiver 2. When unused, connect these

pins to ground.

A9, A10 Input RX1_IN+, RX1_IN− Differential Input for Main Receiver 1. When unused, connect these

pins to ground.

Data Sheet ADRV9009

Rev. A| Page 17 of 128

Pin No. Type Mnemonic Description

A12, A13 Input ORX1_IN+, ORX1_IN− Differential Input for Observation Receiver 1. When unused, connect

these pins to ground.

B1 Input VDDA1P3_RX_RF Observation Receiver Supply.

B7, B8 Input RF_EXT_LO_I/O−,

RF_EXT_LO_I/O+,

Differential External LO Input/Output. If these pins are used for the

external LO, the input frequency must be 2× the desired carrier

frequency. When unused, do not connect these pins.

C1 Input/

output

GPIO_3P3_0 GPIO Pin Referenced to 3.3 V Supply. The alternate function is AUXDAC_4.

Because this pin contains an input stage, the voltage on the pin must

be controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or this pin can be left

floating, programmed as outputs, and driven low.

C2 Input/

output

GPIO_3P3_3 GPIO Pin Referenced to 3.3 V Supply. Because this pin contains an input

stage, the voltage on the pin must be controlled. When unused, this pin

can be tied to ground through a resistor (to safeguard against

misconfiguration), or these pins can be left floating, programmed as

outputs, and driven low.

C13 Input/

output

GPIO_3P3_9 GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_9. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

D1 Input/

output

GPIO_3P3_1 GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_5. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

D2 Input/

output

GPIO_3P3_4 GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_6. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

D13 Input/

output

GPIO_3P3_8 GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_1. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

D14 Input/

output

GPIO_3P3_10 GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_0. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

E1 Input/

output

GPIO_3P3_2 GPIO Pin Referenced to 3.3 V Supply. Because this pin contains an input

stage, the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor (to safeguard against

misconfiguration), or these pins can be left floating, programmed as

outputs, and driven low.

E2 Input/

output

GPIO_3P3_5 GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_7. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

E3 Input/

output

GPIO_3P3_6 GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_8. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

E13 Input/

output

GPIO_3P3_7 GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_2. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

ADRV9009 Data Sheet

Rev. A | Page 18 of 128

Pin No. Type Mnemonic Description

E14 Input/

output

GPIO_3P3_11 GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_3. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

C3 Input VDDA1P3_RX_TX 1.3 V Supply for Transmitter/Receiver Baseband Circuits, Transimpedance

Amplifier (TIA), Transmitter Transconductance (GM), Baseband Filters,

and Auxiliary DACs.

C5, C6 Input VDDA1P3_RF_VCO_LDO RF VCO LDO Supply Inputs. Connect Pin C5 to Pin C6. Use a separate

trace on the PCB back to a common supply point.

C7 Input VDDA1P1_RF_VCO 1.1 V VCO Supply. Decouple this pin with 1 µF.

C8 Input VDDA1P3_RF_LO 1.3 V LO Generator for the RF Synthesizer. This pin is sensitive to

supply noise.

C10 Input VDDA1P3_AUX_VCO_LDO 1.3 V Supply.

C12 Input VDDA_3P3 General-Purpose Output Pull-Up Voltage and Auxiliary DAC Supply

Voltage.

C14 Input/

output

RBIAS Bias Resistor. Tie this pin to ground using a 14.3 kΩ resistor. This pin

generates an internal current based on an external 1% resistor.

D10 Input VDDA1P1_AUX_VCO 1.1 V VCO Supply. Decouple this pin with 1 µF.

E4 Input VDDA1P8_BB 1.8 V Supply for the ADC and DAC.

E5 Input VDDA1P3_BB 1.3 V Supply for the ADC, DAC, and AUXADC.

E7, E8 Input REF_CLK_IN+,

REF_CLK_IN−

Device Clock Differential Input.

E10 Output AUX_SYNTH_OUT Auxiliary PLL Output. When unused, do not connect this pin.

E12 Input VDDA1P8_TX 1.8 V Supply for Transmitter.

F3, F4, F11, E11 Input AUXADC_0 to AUXADC_3 Auxiliary ADC Input. When unused, connect these pins to ground with a

pull-down resistor, or connect directly to ground.

G5 Input VDDA1P3_CLOCK_SYNTH 1.3 V Supply Input for Clock Synthesizer. Use a separate trace on the

PCB back to a common supply point.

G7 Input VDDA1P3_RF_SYNTH 1.3 V RF Synthesizer Supply Input. This pin is sensitive to supply noise.

G8 Input VDDA1P3_AUX_SYNTH 1.3 V Auxiliary Synthesizer Supply Input.

G9 Output RF_SYNTH_VTUNE RF Synthesizer VTUNE Output.

H11 Input/

output

GPIO_12 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

H12 Input/

output

GPIO_11 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

J11 Input/

output

GPIO_13 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

J12 Input/

output

GPIO_10 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

J3 Input/

output

GPIO_18 Digital GPIO, 1.8 V to 2.5 V. The joint test action group (J TAG) function is

TCLK. Because this pin contains an input stage, the voltage on the pin

must be controlled. When unused, this pin can be tied to ground

through a resistor (to safeguard against misconfiguration), or it can be

left floating, programmed as output, and driven low.

J7 Input/

output

GPIO_2 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0.

Because this pin contains an input stage, the voltage on the pin must

be controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

Data Sheet ADRV9009

Rev. A| Page 19 of 128

Pin No. Type Mnemonic Description

J8 Input/

output

GPIO_1 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0. Because

this pin contains an input stage, the voltage on the pin must be

controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

K5 Input/

output

GPIO_5 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TDO. Because this pin

contains an input stage, the voltage on the pin must be controlled.

When unused, this pin can be tied to ground through a resistor (to

safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

K6 Input/

output

GPIO_4 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is

TRST

. Because this pin

contains an input stage, the voltage on the pin must be controlled.

When unused, this pin can be tied to ground through a resistor (to

safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

K7 Input/

output

GPIO_3 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1. Because

this pin contains an input stage, the voltage on the pin must be

controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

K8 Input/

output

GPIO_0 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1. Because

this pin contains an input stage, the voltage on the pin must be

controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or it can be left floating,

programmed as output, and driven low.

K11 Input/

output

GPIO_14 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

K12 Input/

output

GPIO_9 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

L5 Input/

output

GPIO_6 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TDI. Because this pin

contains an input stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor (to safeguard

against misconfiguration), or it can be left floating, programmed as

output, and driven low.

L6 Input/

output

GPIO_7 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TMS. Because this pin

contains an input stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor (to safeguard

against misconfiguration), or it can be left floating, programmed as

output, and driven low.

L11 Input/

output

GPIO_15 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

L12 Input/

output

GPIO_8 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

M10 Input/

output

GPIO_17 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

M11 Input/

output

GPIO_16 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.

H14, J14 Output TX1_OUT+, TX1_OUT− Transmitter 1 Output. When unused, do not connect these pins.

H1, J1 Output TX2_OUT−, TX2_OUT+ Transmitter 2 Output. When unused, do not connect these pins.

ADRV9009 Data Sheet

Rev. A | Page 20 of 128

Pin No. Type Mnemonic Description

J4 Input

RESET

Active Low Chip Reset.

J5 Output GP_INTERRUPT General-Purpose Digital Interrupt Output Signal. When unused, do

not connect this pin.

J6 Input TEST Pin Used for JTAG Boundary Scan. When unused, connect this pin to

ground.

J9 Input/

output

SDIO Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire Mode.

J10 Output SDO Serial Data Output. In SPI 3-wire mode, do not connect this pin.

K3, K4 Input SYSREF_IN+, SYSREF_IN− LVDS Input.

K9 Input SCLK Serial Data Bus Clock.

K10 Input

Serial Data Bus Chip Select, Active Low.

L3, L4 Input

SYNCIN1−

SYNCIN1+

LVDS Input. These pins form the sync signal associated with receiver

channel data on the JESD204B interface. When unused, connect these

pins to ground with a pull-down resistor, or connect these pins directly to

ground.

L7, L10 Input VSSD Digital V

L8, L9 Input VDDD1P3_DIG 1.3 V Digital Core. Connect Pin L8 and Pin L9 together. Use a wide

trace to connect to a separate power supply domain.

L13, L14 Output

SYNCOUT1−

SYNCOUT1+

LVDS Output. These pins form the sync signal associated with transmitter

channel data on the JESD204B interface. When unused, do not connect

these pins.

M1 Input VDDA1P1_CLOCK_VCO 1.1 V VCO Supply. Decouple this pin with 1 µF.

M3, M4 Input

SYNCIN0−

SYNCIN0+

LVDS Input. These pins form the sync signal associated with receiver

channel data on the JESD204B interface. When unused, connect these

pins to ground with a pull-down resistor, or connect these pins directly to

ground.

M5 Input RX1_ENABLE Receiver 1 Enable Pin. When unused, connect this pin to ground with a

pull-down resistor, or connect this pin directly to ground.

M6 Input TX1_ENABLE Transmitter 1 Enable Pin. When unused, connect this pin to ground

with a pull-down resistor, or connect this pin directly to ground.

M7 Input RX2_ENABLE Receiver 2 Enable Pin. When unused, connect this pin to ground with a

pull-down resistor, or connect this pin directly to ground.

M8 Input TX2_ENABLE Transmitter 2 Enable Pin. When unused, connect this pin to ground

with a pull-down resistor, or connect this pin directly to ground.

M12 Input VDD_INTERFACE Input/Output Interface Supply, 1.8 V to 2.5 V.

M13, M14 Output

SYNCOUT0−

SYNCOUT0+

LVDS Output. These pins form the sync signal associated with transmitter

channel data on the JESD204B interface. When unused, do not connect

these pins.

N1 Input VDDA1P3_CLOCK_

VCO_LDO

1.3 V Use Separate Trace to Common Supply Point.

N3, N4 Output SERDOUT3−, SERDOUT3+ RF Current Mode Logic (CML) Differential Output 3. When unused, do

not connect these pins.

N5, N6 Output SERDOUT2−, SERDOUT2+ RF CML Differential Output 2. When unused, do not connect these pins.

N8, P8 Input VDDA1P3_SER 1.3 V Supply for JESD204B Serializer.

N9, P9 Input VDDA1P3_DES 1.3 V Supply for JESD204B Deserializer.

N10, N11 Input SERDIN1−, SERDIN1+ RF CML Differential Input 1. When unused, do not connect these pins.

N13, N12 Input SERDIN0+, SERDIN0− RF CML Differential Input 0. When unused, do not connect these pins.

P1 Output AUX_SYNTH_VTUNE Auxiliary Synthesizer VTUNE Output.

P4, P5 Output SERDOUT1−, SERDOUT1+, RF CML Differential Output 1. When unused, do not connect these

pins.

P6, P7 Output SERDOUT0−,

SERDOUT0+,

RF CML Differential Output 0. When unused, do not connect these

pins.

P11, P12 Input SERDIN3−, SERDIN3+ RF CML Differential Input 3. When unused, do not connect these pins.

P13, P14 Input SERDIN2−, SERDIN2+ RF CML Differential Input 2. When unused, do not connect these pins.

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