3D布局优化：低功耗高效能片上网络THIN研究

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"低功耗和面积有效的片上网络体系结构的3D平面规划" 随着芯片多处理器（CMP）的发展，网络-on-芯片（NoC）架构已成为解决深亚微米技术中延迟问题的有效手段。然而，随着特征尺寸的减小，功率消耗和面积限制成为制约NoC性能的关键因素。在这种背景下，文章提出了基于Triplet的分层互连网络（THIN），这是一种新型的高性能NoC架构。THIN旨在克服传统NoC设计中的功率和面积挑战。文章详细介绍了三种3D布局规划方法，这些方法结合了曼哈顿架构和Y架构的路由策略。这种创新设计旨在同时提高网络性能，降低功耗，并减少THIN的物理面积。通过使用Noxim NoC仿真器进行周期精确的仿真，并利用ORION 2.0能量模型进行评估，作者展示了所提布局方法的优势。与传统的3D网格架构相比，这些方法可以实现最高24.69%的能量节省，并最多减少8.84%的面积。关键词包括"Network-on-Chip"，"THIN"，"Floorplanning"以及"Performance evaluation"，表明研究的重点在于NoC的3D布局规划、THIN架构的性能优化以及功耗和面积效率的评估。具体来说，"Network-on-Chip"是指在单个芯片上集成多个处理单元的通信架构；"THIN"是文章提出的新颖NoC架构，以提高性能和降低功耗；"Floorplanning"涉及到如何在芯片上有效地布置组件，以达到最佳的性能和资源利用率；"Performance evaluation"则是通过仿真和建模来量化设计改进的效果。论文中，作者Licheng Xue、Feng Shia、Weixing Jia和Haroon-Ur-Rashid Khan分别来自中国北京理工大学和巴基斯坦工程与应用科学研究所，他们的工作展示了在物理层面实施THIN不仅是可行的，而且是一种既节能又节省面积的NoC解决方案。通过深入研究和实验，他们证实了THIN在应对功率和面积挑战方面具有显著优势，为未来NoC设计提供了新的方向和参考。这篇文章揭示了3D布局规划在构建低功耗、高效能NoC架构中的关键作用，特别是在THIN架构的应用上。通过巧妙地融合不同的路由架构，提出的3D布局策略成功地平衡了性能、功率和面积之间的关系，为CMP的未来发展提供了新的视角和可能的解决方案。

is 3 GHz. The experimental results show that the power and area

reduction of the router in THIN (4-port, 1 local port and 3 router

connection ports) is 21.46% and 53.51% compared with 2D Mesh,

which has one more router port (5-port, 1 local port and 4 router

connection ports). Fig. 3 plots static metric of NoCs varied with

the number of cores. The amount of links in THIN is less than the

other two NoCs which beneﬁts the power and area reduction of

NoC. Fig. 3b shows that the network diameter of THIN falls in be-

tween that of 2D Mesh and 2D Torus.

3. Floorplanning of THIN

Mesh is widely used in parallel computing platform for its sim-

ple connection and its ease of placement and routing. Researchers

have reached an agreement on the placing and routing method for

Mesh [30]. However, other NoCs (e.g., BFT, Torus, Spidergon, and

THIN) are not widely accepted partly because the ﬂoorplanning

of these NoCs is difﬁcult than Mesh. THIN is physically difﬁcult

to implement because of its triangle periphery edge and diagonal

wires connecting each router. In this section, we used two different

routing architectures including both Manhattan routing architec-

ture and Y-architecture to achieve the placement of the hot pro-

cessing elements and routing of wires in THIN. In order to

decrease the latency, energy dissipation and area requirement,

3D stacking technology was adopted. As shown in Fig. 4, our meth-

ods are explored based on placing processing elements in the same

layer which was closest to the heat sink and leaving cache layers in

all remaining layers for the consideration of heat dissipation. We

integrate multiple layers of Mesh, Torus and THIN networks by

connecting them with a dynamic, Time-Division Multiple-Access

(dTDMA) bus spanning the entire vertical distance of the chip

[31]. In this paper, we ﬁrst present the ﬂoorplanning of the core

layer in THIN, and then demonstrate the cache block and cache

layer ﬂoorplanning method of THIN. We chose 9-core THIN as an

example, because THIN, 3D Mesh and 3D Torus are the same sizes

and have nine processing elements interconnection network.

When researchers discuss the routing algorithm for NoCs, the

routing of packets is performed without any knowledge of ﬂoor-

planning. They assume that the latency and power consumption

of each hop is equal. The equality characteristic of wires implies

wires with the same latency and power consumption. This equal-

ity, however, is established based on the ﬂoorplanning methods.

In this section, we discuss the effect of wires ﬁrst. And then, we

present three methods which utilize both equal and unequal wires

models to connect the routers in the ﬂoorplanning of THIN.

3.1. Wires discussion

In this paper, each processing element is placed as a dedicated

hard block tile. The horizontal distance between two tiles is sup-

posed to be 1.5 mm. According to different routing architectures,

four methods can be used to achieve the triangle shape (fully con-

nected three cores) in THIN. Fig. 5a shows an equilateral triangle

with a side length of 1.732 mm. This type of interconnection can

be easily mapped into Y-architecture. Fig. 5b shows the right trian-

gle, which can be mapped into X-architecture. Wire lengths are dif-

ferent in this routing method. The length of the longest wire is

1:5mm

ﬃﬃﬃ

¼ 2:121 mm. Fig. 5c and 5d presents two solutions

using Manhattan routing architecture. In Fig. 5c, the lengths of

all the wires are equal, and the value is 1.5 mm  1.5 = 2.25 mm.

Due to the link between two routers is made up with three short

wires in different metal layers, vias are inserted to implement

the inter-layer transmission which is shown in Fig. 6. Fig. 5d pre-

sents an unequal length model, in which the long wire has double

Table 1

Static metric of different NoCs with N-core.

Degree Total links Network diameter

THIN 3 3(N-1)/2

log 3

 1

2D mesh 4

2(N-

ﬃﬃﬃﬃ

)2(

ﬃﬃﬃﬃ

-1)

2D torus 4 2N

ﬃﬃﬃﬃ

=2c

Table 2

Power consumption and area requirement of routers with different number of ports.

4-Port 5-Port 6-Port 7-Port

Power (mw) 116.985 148.950 188.681 225.024

Area (

) 73,261 157,585 219,824 292,303

Fig. 3. Static metric comparison.

Fig. 4. Side view of 3D chip with dTDMA bus.

486 L. Xue et al. / Microprocessors and Microsystems 35 (2011) 484–495

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3D布局优化：低功耗高效能片上网络THIN研究

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