镁光 Automotive LPDDR4 SDRAM 数据手册

需积分: 9 31 浏览量更新于2024-07-07 1 收藏 3.72MB PDF 举报

"该文档是镁光公司(Micron)的LPDDR4内存规格书，主要涉及MT53B256M32D1和MT53B512M32D2两种型号的 Automotive LPDDR4 SDRAM。" 在LPDDR4(Mobile Low Power Double Data Rate 4)内存技术中，MT53B256M32D1和MT53B512M32D2是镁光设计的针对汽车应用的高性能、低功耗DRAM芯片。以下是这些芯片的主要特点和功能： 1. **超低电压核心与I/O电源供应**：内存芯片工作在非常低的电压下，VDD1核心电压为1.70V至1.95V，标准值为1.8V；VDD2和VDDQ I/O电源供应为1.06V至1.17V，标准值为1.10V。这显著降低了功耗，对于车载应用尤其重要，因为车辆电池寿命和能源效率至关重要。 2. **频率范围**：支持1600MHz至10MHz的数据速率范围，这意味着数据传输速度可达到每引脚3200MB/s至20MB/s，提供高效能。 3. **16n prefetch DDR架构**：这种架构提高了数据处理速度，预取机制使得内存可以提前读取数据，提高数据传输效率。 4. **双通道分区结构**：通过将内存分为两个独立的通道，降低了读写能量消耗，并减少了平均访问延迟，允许同时进行多个操作。 5. **8个内部银行**：每个通道有8个内部银行，允许并发操作，进一步提升了多任务处理能力。 6. **单数据率CMD/ADR入口**：命令和地址输入以单数据率方式处理，简化了系统设计。 7. **双向/差分数据 strobe**：每个字节线都有一个双向/差分数据strobes信号，确保数据同步和准确传输。 8. **可编程的读写延迟**（RL/WL）和突发长度（BL=16,32）：可以根据系统需求调整读写延迟和突发长度，优化性能。 9. **定向银行刷新**：允许在不影响其他银行操作的情况下对单个银行进行刷新，有利于命令调度。 10. **高数据传输速率**：每个芯片最高可达12.8GB/s（两通道乘以6.4GB/s），提供极高的带宽。 11. **片上温度传感器**：用于控制自刷新速率，确保在不同环境温度下的稳定运行。 12. **部分阵列自刷新**（PASR）：仅对正在使用的内存部分进行刷新，节省能源。 13. **可选择的输出驱动强度**（DS）：根据系统需求调整输出驱动强度，平衡性能和功耗。 14. **时钟停止功能**：在不需要时停止时钟信号，进一步降低功耗。 15. **符合RoHS标准的绿色包装**：无有害物质，环保友好。 16. **可编程VSSQ（ODT）终端**：允许对片上终结器进行编程，以优化信号完整性和系统性能。在标记选项中，提供了两种不同的配置： - MT53B256M32D1：256兆字节x32位（2条x16通道） - MT53B512M32D2：512兆字节x32位（2条x16通道）这些特性使得镁光的 Automotive LPDDR4 SDRAM 芯片适用于对性能和能效有严格要求的汽车电子系统，如高级驾驶辅助系统(ADAS)、车载信息娱乐系统等。

General Description

The 8Gb Mobile Low-Power DDR4 SDRAM (LPDDR4) is a high-speed CMOS, dynamic

random-access memory. The device is internally configured with 2 x16 channels, each

channel having 8-banks.

Each of the x16’s 536,870,912-bit banks is organized as 32,768 rows by 1024 columns by

16 bits.

General Notes

Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be inter-

preted as any or all DQ collectively, unless specifically stated otherwise.

“DQS” and “CK” should be interpreted as DQS_t, DQS_c and CK_t, CK_c respectively,

unless specifically stated otherwise. “CA” includes all CA pins used for a given density.

Complete functionality may be described throughout the entire document. Any page or

diagram may have been simplified to convey a topic and may not be inclusive of all re-

quirements.

Any specific requirement takes precedence over a general statement.

Any functionality not specifically stated herein is considered undefined, illegal, is not

supported, and will result in unknown operation.

Micron Confidential and Proprietary Preliminary

200b: x32 Automotive LPDDR4 SDRAM

General Description

PDF: 09005aef86275f79

200b_z91m-sdp_ddp_auto_lpddr4.pdf – Rev. C 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 2: Ball/Pad Descriptions

Symbol Type Description

CK_t_A, CK_c_A,

CK_t_B, CK_c_B

Input Clock: CK_t and CK_c are differential clock inputs. All address, command and control

input signals are sampled on positive edge of CK_t and the negative edge of CK_c. AC

timings for CA parameters are referenced to clock. Each channel (A, B) has its own

clock pair.

CKE0_A, CKE1_A,

CKE0_B, CKE1_B

Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals,

input buffers, and output drivers. Power-saving modes are entered and exited via CKE

transitions. CKE is sampled at the rising edge of CK.

CS0_A, CS1_A, CS0_B,

CS1_B

Input Chip select: Each channel (A, B) has its own CS signals.

CA[5:0]_A, CA[5:0]_B Input Command/address inputs: Provide the command and address inputs according to

the command truth table. Each channel (A, B) has its own CA signals.

ODT_CA_A,

ODT_CA_B

Input CA ODT Control: The ODT_CA pin is used in conjunction with the mode register to

turn on/off the on-die termination for CA pins. It is bonded to V

DD2

within the pack-

age, or at the package ball, for the terminating rank, and the non-terminating ranks

are bonded to V

(or left floating with a weak pull-down on the DRAM die). The ter-

minating rank is the DRAM that terminates the CA bus for all die on the same channel.

DQ[15:0]_A,

DQ[15:0]_B

I/O Data input/output: Bidirectional data bus.

DQS[1:0]_t_A,

DQS[1:0]_c_A,

DQS[1:0]_t_B,

DQS[1:0]_c_B

I/O Data strobe: DQS_t and DQS_c are bi-directional differential output clock signals

used to strobe data during a READ or WRITE. The data strobe is generated by the

DRAM for a READ and is edge-aligned with data. The data strobe is generated by the

SoC memory controller for a WRITE and is trained to precede data. Each byte of data

has a data strobe signal pair. Each channel (A, B) has its own DQS_t and DQS_c strobes.

DMI[1:0]_A,

DMI[1:0]_B

I/O Data Mask/Data Bus Inversion: DMI is a dual use bi-directional signal used to indi-

cate data to be masked, and data which is inverted on the bus. For data bus inversion

(DBI), the DMI signal is driven HIGH when the data on the data bus is inverted, or driv-

en LOW when the data is in its normal state. DBI can be disabled via a mode register

setting. For data mask, the DMI signal is used in combination with the data lines to

indicate data to be masked in a MASK WRITE command (see the Data Mask (DM) and

Data Bus Inversion (DBI) sections for details). The data mask function can be disabled

via a mode register setting. Each byte of data has a DMI signal. Each channel has its

own DMI signals.

ZQ0, ZQ1 Reference ZQ Calibration Reference: Used to calibrate the output drive strength and the ter-

mination resistance. There is one ZQ pin per die. The ZQ pin shall be connected to

DDQ

through a 240Ω ±1% resistor.

DDQ

, V

DD1

, V

DD2

Supply Power supplies: Isolated on the die for improved noise immunity.

Supply Ground Reference: Power supply ground reference.

RESET_n Input RESET: When asserted LOW, the RESET pin resets both channels of the die.

DNU – Do not use: Must be grounded or left floating.

NC – No connect: Not internally connected.

Micron Confidential and Proprietary Preliminary

200b: x32 Automotive LPDDR4 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef86275f79

200b_z91m-sdp_ddp_auto_lpddr4.pdf – Rev. C 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

剩余253页未读，继续阅读

智芯创新001

粉丝: 15
资源: 12

镁光 Automotive LPDDR4 SDRAM 数据手册

LPDDR4内存技术中MT53B256M32D1和MT53B512M32D2型号的 Automotive LPDDR4 SDRAM 在性能与功耗上有哪些优势？

针对汽车应用，LPDDR4内存技术中的MT53B256M32D1和MT53B512M32D2型号SDRAM在工作频率、能效、数据传输速度及温度控制方面具有哪些特点和优势？请结合《镁光 Automotive LPDDR4 SDRAM 数据手册》进行详细说明。

MT53E512M32D2-LPDDR4 2GB.pdf

DRAM技术精解(中文) DDR3-DDR4-DDR5-LPDDR3-LPDDR4-LPDDR5.pdf

Micron-MT46H16M32LFB5-6 ATC.pdf

Micron-MT46H16M32LFB5-6 IT.pdf

lpddr4-design-guidelines.pdf

Micron-MT46H16M32LFB5-6 ATC TR.pdf

MT53E256M32D2DS-053.pdf

designcon19-analyzing-lpddr4x-interfaces-cp.pdf

最新资源