PCIe 1.1规范详解：架构与接口全解析

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PCIE 1.1规范是PCI Express (Peripheral Component Interconnect Express) 的基础规格版本，发布于2005年3月28日。该规范详细定义了PCI Express架构、接口特性、 Fabric（总线结构）管理和设计及构建符合PCI Express标准的系统和外设所需的编程接口。PCIe 1.1标准旨在提供一种高速、低延迟的点对点连接技术，用于取代传统的PCI（Peripheral Component Interconnect）接口，以满足现代计算机系统对数据传输速率和带宽的需求。在PCI Express 1.1规范中，关键知识点包括： 1. **PCI Express架构**：它定义了PCIe的物理层、逻辑层和功能层，包括信道配置、信号传输、时钟管理以及热插拔功能等，确保系统的可靠性和扩展性。 2. **接口特性**：包括接口速度、带宽、电压标准和电源管理，以及错误检测和恢复机制，如错包检测（Error Checking and Correction, ECC）、流量控制等，以提高数据传输的效率和准确性。 3. **Fabric管理**：描述了PCIe Fabric如何组织，包括根端口（Root Port）、端口、扩展器（Switch）和链路（Link）等组件，以及如何通过不同的配置模式进行管理。 4. **编程接口**：为硬件开发者提供了详细的接口描述，包括配置空间访问、中断处理、状态机操作等，使得设计者能够根据规范创建兼容的硬件设备和驱动程序。 5. **修订历史**：从1.0版本的初始发布到1.1版本的更新，强调了对之前发现的错误和工程变更（Errata）的整合，确保了技术的稳定性和一致性。 6. **免责声明**：PCI-SIG（PCI Special Interest Group）明确声明，该规范提供无任何保证，包括但不限于商品质量、不侵权、特定用途适用性或因提案、规格或样例而产生的其他任何保证。用户在使用时需自行承担风险，并应直接联系PCI-SIG获取最新版本和更新信息。 7. **获取支持**：文档提供了PCI-SIG的联系方式，包括网站、电子邮件和电话，以便于获取最新规范版本和解决相关问题。 PCIe 1.1规范是IT工程师必备的参考材料，对于理解和设计高性能、低延迟的PCIe系统至关重要，同时它也反映了当时的行业标准发展趋势，为后续的PCIe版本迭代奠定了基础。

PCI EXPRESS BASE SPECIFICATION, REV 1.1

TABLE 5-1: SUMMARY OF PCI EXPRESS LINK POWER MANAGEMENT STATES .......................... 263

TABLE 5-3: RELATION BETWEEN POWER MANAGEMENT STATES OF LINK AND COMPONENTS.. 268

TABLE 5-5: ENCODING OF THE ASPM SUPPORT FIELD .............................................................. 296

ABLE 5-7: DESCRIPTION OF THE SLOT CLOCK CONFIGURATION FIELD..................................... 296

ABLE 5-9: DESCRIPTION OF THE COMMON CLOCK CONFIGURATION FIELD.............................. 296

TABLE 5-11: ENCODING OF THE L0S EXIT LATENCY FIELD........................................................ 297

TABLE 5-13: ENCODING OF THE L1 EXIT LATENCY FIELD ......................................................... 297

TABLE 5-15: ENCODING OF THE ENDPOINT L0S ACCEPTABLE LATENCY FIELD ......................... 298

ABLE 5-17: ENCODING OF THE ENDPOINT L1 ACCEPTABLE LATENCY FIELD ........................... 298

ABLE 5-19: ENCODING OF THE ASPM CONTROL FIELD ........................................................... 298

TABLE 5-21: POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS....................................... 301

TABLE 6-1: ERROR MESSAGES ................................................................................................... 310

TABLE 6-3: PHYSICAL LAYER ERROR LIST................................................................................. 322

ABLE 6-5: DATA LINK LAYER ERROR LIST............................................................................... 322

ABLE 6-7: TRANSACTION LAYER ERROR LIST .......................................................................... 323

TABLE 6-9: ELEMENTS OF HOT-PLUG......................................................................................... 353

TABLE 6-11: ATTENTION INDICATOR STATES............................................................................. 355

TABLE 6-13: POWER INDICATOR STATES.................................................................................... 356

TABLE 7-1: ENHANCED CONFIGURATION ADDRESS MAPPING.................................................... 382

TABLE 7-3: REGISTER (AND REGISTER BIT-FIELD) TYPES.......................................................... 388

TABLE 7-5: COMMAND REGISTER............................................................................................... 391

TABLE 7-7: STATUS REGISTER.................................................................................................... 392

TABLE 7-9: SECONDARY STATUS REGISTER ............................................................................... 399

TABLE 7-11: BRIDGE CONTROL REGISTER ................................................................................. 401

TABLE 7-13: POWER MANAGEMENT CAPABILITIES REGISTER ADDED REQUIREMENTS ............. 403

TABLE 7-15: POWER MANAGEMENT STATUS/CONTROL REGISTER ADDED REQUIREMENTS ...... 404

TABLE 7-17: PCI EXPRESS CAPABILITY LIST REGISTER............................................................. 406

TABLE 7-19: PCI EXPRESS CAPABILITIES REGISTER .................................................................. 406

TABLE 7-21: DEVICE CAPABILITIES REGISTER ........................................................................... 409

TABLE 7-23: DEVICE CONTROL REGISTER.................................................................................. 414

ABLE 7-25: DEVICE STATUS REGISTER..................................................................................... 421

TABLE 7-27: LINK CAPABILITIES REGISTER ............................................................................... 423

ABLE 7-29: LINK CONTROL REGISTER...................................................................................... 426

ABLE 7-31: LINK STATUS REGISTER......................................................................................... 430

TABLE 7-33: SLOT CAPABILITIES REGISTER............................................................................... 432

TABLE 7-35: SLOT CONTROL REGISTER ..................................................................................... 435

ABLE 7-37: SLOT STATUS REGISTER ........................................................................................ 439

TABLE 7-39: ROOT CONTROL REGISTER..................................................................................... 443

ABLE 7-41: ROOT CAPABILITIES REGISTER .............................................................................. 444

TABLE 7-42: ROOT STATUS REGISTER ....................................................................................... 445

TABLE 7-44: PCI EXPRESS ENHANCED CAPABILITY HEADER .................................................... 447

ABLE 7-46: ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER ........................ 450

TABLE 7-48: UNCORRECTABLE ERROR STATUS REGISTER......................................................... 451

ABLE 7-50: UNCORRECTABLE ERROR MASK REGISTER............................................................ 453

ABLE 7-52: UNCORRECTABLE ERROR SEVERITY REGISTER...................................................... 454

ABLE 7-54: CORRECTABLE ERROR STATUS REGISTER.............................................................. 455

PCI EXPRESS BASE SPECIFICATION, REV 1.1

TABLE 7-56: CORRECTABLE ERROR MASK REGISTER ................................................................ 456

TABLE 7-58: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER ................................. 457

TABLE 7-60: HEADER LOG REGISTER......................................................................................... 458

ABLE 7-62: ROOT ERROR COMMAND REGISTER....................................................................... 459

ABLE 7-64: ROOT ERROR STATUS REGISTER............................................................................ 462

TABLE 7-66: ERROR SOURCE IDENTIFICATION REGISTER........................................................... 464

TABLE 7-68: VIRTUAL CHANNEL ENHANCED CAPABILITY HEADER........................................... 466

TABLE 7-70: PORT VC CAPABILITY REGISTER 1........................................................................ 467

ABLE 7-72: PORT VC CAPABILITY REGISTER 2 ........................................................................ 469

ABLE 7-74: PORT VC CONTROL REGISTER............................................................................... 469

TABLE 7-76: PORT VC STATUS REGISTER.................................................................................. 470

TABLE 7-78: VC RESOURCE CAPABILITY REGISTER .................................................................. 471

TABLE 7-80: VC RESOURCE CONTROL REGISTER...................................................................... 474

ABLE 7-82: VC RESOURCE STATUS REGISTER......................................................................... 477

ABLE 7-84: DEFINITION OF THE 4-BIT ENTRIES IN THE VC ARBITRATION TABLE..................... 478

TABLE 7-86: LENGTH OF THE VC ARBITRATION TABLE............................................................. 478

TABLE 7-88: LENGTH OF PORT ARBITRATION TABLE................................................................. 480

TABLE 7-90: DEVICE SERIAL NUMBER ENHANCED CAPABILITY HEADER.................................. 482

TABLE 7-92: SERIAL NUMBER REGISTER.................................................................................... 482

TABLE 7-94: ROOT COMPLEX LINK DECLARATION ENHANCED CAPABILITY HEADER............... 485

TABLE 7-95: ELEMENT SELF DESCRIPTION REGISTER ................................................................. 486

TABLE 7-96: LINK DESCRIPTION REGISTER................................................................................ 487

TABLE 7-97: LINK ADDRESS FOR LINK TYPE 1........................................................................... 490

TABLE 7-98: ROOT COMPLEX INTERNAL LINK CONTROL ENHANCED CAPABILITY HEADER...... 491

TABLE 7-99: ROOT COMPLEX LINK CAPABILITIES REGISTER..................................................... 492

TABLE 7-100: ROOT COMPLEX LINK CONTROL REGISTER ......................................................... 494

TABLE 7-101: ROOT COMPLEX LINK STATUS REGISTER ............................................................ 496

TABLE 7-102: POWER BUDGETING ENHANCED CAPABILITY HEADER ........................................ 497

TABLE 7-104: POWER BUDGETING DATA REGISTER................................................................... 499

TABLE 7-106: POWER BUDGET CAPABILITY REGISTER .............................................................. 501

ABLE 7-108: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION ENHANCED

CAPABILITY HEADER........................................................................................................... 502

ABLE 7-109: MFVC ENHANCED CAPABILITY HEADER............................................................ 505

ABLE 7-110: PORT VC CAPABILITY REGISTER 1...................................................................... 506

TABLE 7-111: PORT VC CAPABILITY REGISTER 2...................................................................... 507

TABLE 7-112: PORT VC CONTROL REGISTER............................................................................. 508

ABLE 7-113: PORT VC STATUS REGISTER................................................................................ 509

TABLE 7-114: VC RESOURCE CAPABILITY REGISTER ................................................................ 509

ABLE 7-115: VC RESOURCE CONTROL REGISTER .................................................................... 511

TABLE 7-116: VC RESOURCE STATUS REGISTER ....................................................................... 513

TABLE 7-117: LENGTH OF FUNCTION ARBITRATION TABLE....................................................... 515

ABLE 7-118: VENDOR-SPECIFIC ENHANCED CAPABILITY HEADER .......................................... 517

TABLE 7-119: VENDOR-SPECIFIC HEADER ................................................................................. 518

ABLE 7-120: RCRB HEADER ENHANCED CAPABILITY HEADER .............................................. 519

ABLE 7-121: VENDOR ID AND DEVICE ID................................................................................ 520

ABLE 7-122: RCRB CAPABILITIES ........................................................................................... 520

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