STM32-F3/F4/F7/H7低电压64Mbit SPI闪存M25P64开发预览

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电子-M25P64.pdf文档介绍了STM32-F3/F4/F7/H7系列单片机/嵌入式系统中的一款关键组件——M25P64，这是一款64兆位（64Mbit）低电压串行闪存内存。这款产品的主要特点如下： 1. 存储容量：M25P64提供了64Mbit的非易失性存储空间，非常适合对存储需求较高的应用，如嵌入式系统、工业控制或物联网设备。 2. 编程速度：它支持快速编程功能，最多可将256字节的数据在1.4毫秒内写入页面（典型值），这对于实时性和效率至关重要的项目来说是非常关键的特性。 3. 数据管理：除了页面编程，M25P64还支持更大的数据块操作，包括512Kbit的扇区擦除和整个64Mbit的批量擦除，便于管理大规模数据。 4. 电源兼容性：这款闪存内存工作于2.7至3.6伏的单一电源范围内，确保了广泛的供电环境适应性。 5. 接口兼容性：M25P64采用了标准的SPI（Serial Peripheral Interface）接口，使得与各种微控制器集成变得简单，最大支持50MHz的时钟速率。 6. 电子签名：为了保证产品的兼容性和身份验证，M25P64具有两种电子签名，分别是JEDEC标准的两字节签名（2017h）和为后向兼容设计的一字节RES指令签名（16h）。 7. 数据持久性：M25P64能够承受超过100,000次的每扇区擦除和编程循环，保证了长期的数据存储稳定性，数据保留时间超过20年。文档还包含了封装形式，如VDFPN8（ME）和SO16（MF），尺寸分别为8x6毫米（MLP8）和300mil宽度，以及相关的连接图示（如逻辑图、信号名称表和引脚连接图）来帮助用户理解其内部结构和如何在电路板上正确配置。此外，文档还提供了一个详细的信号描述部分，包括串行数据输出Q、输入D、时钟C、片选S、保持HOLD和写保护W等控制信号的定义，这对于理解和使用这款闪存内存的硬件工程师来说是极其重要的参考信息。总结来说，电子-M25P64.pdf是一份详细介绍STM32-F3/F4/F7/H7系列单片机中一款高性能、低功耗的串行闪存记忆体的产品规格和技术资料，涵盖了存储容量、编程速度、接口兼容性、电子签名、数据持久性以及引脚信号等核心知识点，对于设计和开发基于这些平台的嵌入式解决方案非常实用。

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M25P64

SPI MODES

These devices can be driven by a microcontroller

with its SPI peripheral running in either of the two

following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on

the rising edge of Serial Clock (C), and output data

is available from the falling edge of Serial Clock

(C).

The difference between the two modes, as shown

in Figure 6., is the clock polarity when the bus

master is in Stand-by mode and not transferring

data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. Bus Master and Memory Devices on the SPI Bus

Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 6. SPI Modes Supported

AI03746D

Bus Master

(ST6, ST7, ST9,

ST10, Others)

SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

HOLD

AI01438B

MSB

CPHA

CPOL

MSB

M25P64

8/38

OPERATING FEATURES

Page Programming

To program one data byte, two instructions are re-

quired: Write Enable (WREN), which is one byte,

and a Page Program (PP) sequence, which con-

sists of four bytes plus data. This is followed by the

internal Program cycle (of duration t

To spread this overhead, the Page Program (PP)

instruction allows up to 256 bytes to be pro-

grammed at a time (changing bits from 1 to 0), pro-

vided that they lie in consecutive addresses on the

same page of memory.

Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to

be reset from 1 to 0. Before this can be applied, the

bytes of memory need to have been erased to all

1s (FFh). This can be achieved either a sector at a

time, using the Sector Erase (SE) instruction, or

throughout the entire memory, using the Bulk

Erase (BE) instruction. This starts an internal

Erase cycle (of duration t

or t

The Erase instruction must be preceded by a Write

Enable (WREN) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status

BE) can be achieved by not waiting for the worst

case delay (t

, t

, or t

). The Write In

Progress (WIP) bit is provided in the Status Regis-

ter so that the application program can monitor its

value, polling it to establish when the previous

Write cycle, Program cycle or Erase cycle is com-

plete.

Active Power and Standby Power Modes

When Chip Select (S) is Low, the device is select-

ed, and in the Active Power mode.

When Chip Select (S

) is High, the device is dese-

lected, but could remain in the Active Power mode

until all internal cycles have completed (Program,

Erase, Write Status Register). The device then

goes in to the Standby Power mode. The device

consumption drops to I

CC1

Status Register

The Status Register contains a number of status

and control bits that can be read or set (as appro-

priate) by specific instructions.

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write Status

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

BP2, BP1, BP0 bits. The Block Protect (BP2,

BP1, BP0) bits are non-volatile. They define the

size of the area to be software protected against

Program and Erase instructions.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W

) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W

)

signal allow the device to be put in the Hardware

Protected mode. In this mode, the non-volatile bits

of the Status Register (SRWD, BP2, BP1, BP0)

become read-only bits.

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