TMS320C6000 DSP EMIF参考指南：SDRAM与异步接口详解

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"DM642 EMIF参考手册是针对TMS320C6000 DSP家族中外部内存接口（EMIF）的操作进行详细阐述的文档。该手册覆盖了TMS320C620x/C670x、TMS320C621x/C671x以及TMS320C64x EMIF的独特操作和寄存器。主要内容包括概述、SDRAM接口、SBSRAM接口、异步接口、重置EMIF、保持接口、访问EMIF寄存器时的边界条件、时钟输出使能、仿真挂起操作和电源关闭等章节。" 在TMS320C6000 DSP系列中，外部内存接口（EMIF）是连接外部存储设备的关键部分，如SDRAM和静态RAM。本参考手册提供了关于如何操作这些接口及其独特功能的详细指南。 1. **概述**：这部分介绍了EMIF的基本概念，包括命令之间的时间间隔，以及如何通过EMIF与不同类型的内存设备交互。 2. **SDRAM接口**：SDRAM接口详细说明了初始化过程、页边界的监控、刷新模式、SDRAM的去激活（DCAB/DEAC）和激活（ACTV）。这些内容对于确保SDRAM的正确运行和数据完整性至关重要。 3. **SBSRAM接口**：这部分涉及到同步背板SRAM的接口，解释了如何与这种类型的内存进行通信。 4. **异步接口**：异步接口部分描述了可编程ASRAM参数、异步读写操作，以及如何处理Ready输入信号。此外，还特别指出C620x/C670x DSP非法访问异步内存的问题。 5. **重置EMIF**：讨论了在重置过程中EMIF时钟的有效性，以及与TMS320C62x/C67x和TMS320C64x EMIF的重置相关的考虑因素。 6. **保持接口**：这部分涉及保持信号对EMIF操作的影响，包括在不同DSP型号中的应用。 7. **访问EMIF寄存器的边界条件**：这部分警告用户在访问EMIF寄存器时应注意的限制和潜在问题。 8. **时钟输出使能**：解释了如何控制和管理EMIF的时钟输出，这对于优化系统性能和降低功耗至关重要。 9. **仿真挂起操作**：描述了在仿真模式下EMIF如何响应挂起命令，这对于调试和测试过程非常有用。 10. **电源关闭**：讨论了EMIF的电源管理功能，包括如何在不使用时降低功耗。该手册是开发基于TMS320C6000 DSP系统的硬件工程师和软件开发者的重要参考资料，他们需要理解和配置外部存储器接口以实现高效的数据处理。通过深入理解这些章节，读者将能够有效地利用EMIF特性来设计可靠的嵌入式系统。

SDRAM Interface

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Table 1-3. Truth Table for SDRAM Commands

SDRAM: CKE CS RAS CAS W A[19:16] A[15:11] A10 A[9:0]

16-bit

EMIF:

(1)

SDCKE CE SDRAS SDCAS SDWE EA[20:17]

(2)

EA[16:12] EA11 EA[10:1]

32-bit

EMIF:

(1)

SDCKE

(3)

CE SDRAS SDCAS SDWE EA[21:18]

(4)

EA[17:13] EA12

(5)

EA[11:2]

(6)

64-bit

EMIF:

(1)

SDCKE CE SDRAS SDCAS SDWE EA[22:19]

(2)

EA[18:14] EA13 EA[12:3]

(7)

ACTV H L L H H 0001b Bank/Row Row Row

0000b

(4)

READ H L H L H X Bank/ L Column

Column

WRT H L H L L X Bank/ L Column

Column

MRS H L L L L L L/Mode Mode Mode

DCAB H L L H L X X H X

DEAC H L L H L X Bank/X L X

REFR H L L L H X X X X

SLFREFR L L L L H X X X X

(1)

16-bit EMIF includes C64x EMIFB; 32-bit EMIF includes all C62x/C67x EMIF, both 32-bit and 16-bit interfaces; 64-bit EMIF

includes C64x EMIFA, both 64-bit and 32-bit interfaces.

(2)

For C64x DSP, upper address bits are used during ACTV to indicate non-PDT (0001b) vs. PDT (0000b) access. During all other

accesses, address bits indicated with X hold previous value.

(3)

SDCKE does not exist on C62x/C67x DSP.

(4)

For C62x/C67x DSP, upper address bits are reserved for future use. Undefined.

(5)

SDA10 is used on C620x/C670x DSP. EA12 is used on C621x/C671x DSP.

(6)

EMIF address numbering for the C6712/C6712C 16-bit EMIF begins with EA2 to maintain signal name compatibility with the

C62x/C67x 32-bit EMIF.

(7)

EMIF address numbering for the C64x 32-bit EMIFA begins with EA3 to maintain signal name compatibility with the C64x 64-bit

EMIFA.

Overview 16 SPRU266E – April 2008

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SDRAM Interface

Table 1-4. TMS320C6000 SDRAM Signal Descriptions

SDRAM

EMIF Signal Signal SDRAM Function

BEx DQMx Data/output mask. DQM is an input/output buffer control signal. When high, it disables writes

and places outputs in the high impedance state during reads. DQM has a 2-CLK-cycle latency

on reads and a 0-CLK-cycle latency on writes. DQM pins serve as byte strobes and are

connected to BE outputs.

CE3, CE2, CS Chip select and command enable. CS must be active (low) for a command to be clocked into

CE1

(1)

, or CE0 the SDRAM. CE1 does not support SDRAM on C620x/C670x DSP.

CLKOUT2 CLK SDRAM clock input. Runs at 1/2 the CPU clock rate. Used for synchronous memory interface

on the C6202(B)/C6203(B)/C6204/C6205 DSP.

ECLKOUT CLK SDRAM clock input. Used for synchronous memory interface on the C621x/C671x/C64x DSP.

For C6713 DSP, runs at either ECLKIN or SYSCLK3 (programmable divide-down clock with

PLL output as reference clock), configurable using EKSRC bit in DEVCFG. For C621x/C671x

DSP, runs at ECLKIN rate. For C64x DSP, ECLKOUT1 is used. ECLKOUT1 runs at EMIF input

clock rate (ECLKIN, CPU/4 clock, or CPU/6 clock).

SDA10

(2)

A10 Address line A10/autoprecharge disable. Serves as a row address bit during ACTV commands

and also disables the autoprecharging function of SDRAM. (C620x/C670x DSP only)

SDCAS CAS Column address strobe and command Input. Latched by the rising edge of CLK to determine

current operation. Valid only if CS is active (low) during that clock edge.

SDCKE

(3)

CKE CKE clock enable. For C64x DSP, SDCKE is connected to CKE to minimize SDRAM power

consumption when self-refresh mode is enabled. For C62x/C67x SDRAM interface, CKE is tied

high (on the SDRAM device) since the Self Refresh command is not supported.

SDCLK CLK SDRAM clock input. Runs at 1/2 the CPU clock rate. Used for SDRAM interface on

C6201/C6701 DSP.

SDRAS RAS Row address strobe and command input. Latched by the rising edge of CLK to determine

current operation. Valid only if CS is active (low) during that clock edge.

SDWE WE Write strobe and command input. Latched by the rising edge of CLK to determine current

operation. Valid only if CS is active (low) during that clock edge.

(1)

For C620x/C670x DSP, CE1 does not support SDRAM.

(2)

SDA10 is used on C620x/C670x DSP. EA12 is used on C621x/C671x DSP. EA13 is used on C64x EMIFA; EA11 is used on

C64x EMIFB.

(3)

SDCKE exists on C64x DSP only.

SPRU266E – April 2008 Overview 17

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