16位无符号整数除法器设计报告：挑战与突破【GROUP 03】

Research Project 16-bit Unsigned Integer Divider Design Report GROUP 03 Hu Jiani Tao Guanhong Wang Zisi Date: 2012-1-14 In Verilog HDL language, although there are division instructions, the divisor in the division operation must be a power of 2, so it is impossible to achieve division with any integer divisor, which greatly limits its application. Moreover, most synthesis tools cannot synthesize satisfactory results for the division operation, and some cannot even synthesize it. The task of our group in this project is to design a 16-bit unsigned integer divider on the xilinx Spartan-3 experimental platform based on the previous LCDF experiment, where the dividend and divisor can be any 16-bit unsigned integer, and obtain the quotient and remainder. When the divisor is zero, an error message is prompted. Design Description: A. Design Development Environment Experimental Platform: xilinx Spartan-3 Development Environment: Xilinx ISE Hardware Description Language: Verilog HDL B. Input-output Interaction Selection Input: Buttons and toggle switches on the Spartan-3 experimental platform Output: Output of the four-digit 7-segment display module C. Core Module Design—Divider For unsigned integers without a sign;...