(1)
PARAMETER
TEST
CONDITIONS
MIN NOM MAX UNIT
SGMII TRANSMITTER AC TIMING
Clock signal duty cycle at 625 MHz 48 52 %
T
rise
Vod Rise Time 100 200 ps
T
fall
Vod Fall Time 100 200 ps
Jitter Output jitter 200 320
(7)
ps
25 MHz CRYSTAL REQUIREMENTS
Frequency 25 MHz
Frequency Tolerance and Stability Over temperature and aging –100 100 ppm
Equivalent Series Resistance 50 Ω
OUTPUT CLOCK TIMING (CLKOUT)
Frequency 25 MHz
Duty Cycle ( With crystal attached) 45 55 %
Rise / Fall Time (10% - 90%) 2.5 ns
Jitter (RMS) (Slave Mode, MAC Iinterface : SGMII) 5 ps
Jitter (RMS) (Master Mode, MAC Iinterface : SGMII) 2.4 ps
Jitter (RMS) (Slave Mode, MAC Interface : RGMII) 11 ps
Jitter (RMS) (Master Mode, MAC Interface : RGMII) 15 ps
Sleep Entry and Wake-Up
WAKE LOW to Sleep Entry; INH Transition LOW
Normal Mode,
MDI_Energy =
FALSE sleep_en =
TRUE
64 85 us
sleep_en = True to Sleep Entry; INH Transition LOW (master
mode)
Normal Mode,
WAKE = LOW,
MDI_Energy =
FALSE
5 85 us
sleep_en = True to Sleep Entry; INH Transition LOW (slave
mode)
Normal Mode,
WAKE = LOW,
MDI_Energy =
FALSE
5000 us
MDI Energy Loss to Sleep Entry; INH Transition LOW
Normal Mode,
WAKE = LOW,
sleep_en = TRUE
5 ms
Local Wake-Up Pulse Duration (on Wake pin)
Sleep Mode, WAKE
pin
80 µs
Send-S/Send-T pattern duration for wake up from MDI Sleep Mode, Slave 1.25 ms
Local Wake-Up; INH Transition HIGH
Sleep Mode, rising
edge of WAKE pin
to rising edge of
INH
85 us
Tolerable differential noise level on MDI for PHY to stay in sleep
mode
Sleep Mode 200 mV pk-pk
Link-partner's VOD for valid wake-up (for 5m cable) Sleep Mode 840 mV pk-pk
(1) Ensured by production test or characterization or design.
(2) No supply sequencing constraint across power rails
(3) In case OSC clock is delayed, additional reset is needed post Osc clock stablisation
(4) Refer register[0x0430] for programmability of RX and TX delay codes
(5) PHY provides internal delays on TX_CLK to TX_D[3:0] to add additional skew upto 2 ns. Refer to register[0x0430] for programmability
(6) Max rise/fall time of 8ns is supported for duty cycle of 40% to 55%. Max rise/fall time will be 6 ns for duty cycle of 40% to 60%
DP83TG720S-Q1
SNLS604D – SEPTEMBER 2020 – REVISED MARCH 2021
www.ti.com
16 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DP83TG720S-Q1
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