X5045 CPU监控器：集成SPI EEPROM、看门狗与电源管理
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更新于2024-07-28
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"X5045是一款集成度极高的微控制器监控芯片，它结合了4KB的SPI EEPROM、看门狗定时器、上电复位控制、电源电压监控以及块锁保护串行EEPROM内存等多种功能，适用于需要这些功能的MCU控制电路。"
X5045芯片详解：
这款器件是Intersil公司生产的一款产品，型号包括X5043和X5045，两者都是4Kbit（512x8Bit）的CPU监控器，其中X5045具有更丰富的功能。它主要设计用于降低系统成本，减少电路板空间需求，并提高系统的可靠性。
1. **上电复位控制**：
当设备接通电源时，上电复位电路会被激活，保持RESET/RESET信号持续一段时间。这个功能使得电源供应和振荡器有足够的时间稳定下来，确保在处理器执行代码之前，系统状态已达到安全运行条件。
2. **看门狗定时器**：
看门狗定时器是一个独立的保护机制，用于防止微控制器出现故障。如果微控制器在预设的超时间隔内未能重新启动定时器，X5045将激活RESET/RESET信号，强制系统复位，从而防止系统进入不稳定的运行状态。
3. **电源电压监控**：
X5045可以监测电源电压，当电压低于安全阈值时，它会触发复位信号，以保护系统不受电源波动的影响。
4. **SPI EEPROM**：
芯片内置的4KB SPI EEPROM允许用户存储配置信息或程序数据。SPI（串行外设接口）是一种低速但高效的串行通信协议，适用于与微控制器进行数据交换，特别是在存储小量数据时非常实用。
5. **块锁保护**：
块锁保护功能可以防止EEPROM中的数据被未经授权的访问或修改，确保数据的安全性。
6. **封装与应用**：
X5045通常采用SOP8或DIP8封装，适用于各种嵌入式系统、工业控制、消费电子以及任何需要可靠电源管理与数据存储的应用场景。
X5045芯片通过集成多种关键功能，为微控制器系统提供了一种高效且可靠的解决方案，能够确保系统在复杂环境下的稳定性和安全性。在设计使用时，需根据具体应用需求设置合适的参数，如看门狗定时器的超时时间、电源电压监控阈值等，以实现最佳的系统性能。
5
FN8126.2
March 16, 2006
Pin Configuration
Pin Descriptions
Serial Output (SO)
SO is a push/pull serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by the
falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this pin.
Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data input
and output. Opcodes, addresses, or data present on the SI
pin is latched on the rising edge of the clock input, while data
on the SO pin changes after the falling edge of the clock
input.
Chip Select (CS/WDI)
When CS is high, the X5043, X5045 are deselected and the
SO output pin is at high impedance and, unless an internal
write operation is underway, the X5043, X5045 will be in the
standby power mode. CS
low enables the X5043, X5045,
placing it in the active power mode. It should be noted that
after power-up, a high to low transition on CS
is required prior
to the start of any operation.
Write Protect (WP)
When WP is low, nonvolatile writes to the X5043, X5045 are
disabled, but the part otherwise functions normally. When
WP
is held high, all functions, including non volatile writes
operate normally. WP
going low while CS is still low will
interrupt a write to the X5043, X5045. If the internal write
cycle has already been initiated, WP
going low will have no
affect on a write.
Reset (RESET, RESET)
X5043, X5045, RESET/RESET is an active low/HIGH, open
drain output which goes active whenever V
CC
falls below the
minimum V
CC
sense level. It will remain active until V
CC
rises above the minimum V
CC
sense level for 200ms.
RESET
/RESET also goes active if the Watchdog timer is
enabled and CS
remains either high or low longer than the
Watchdog time out period. A falling edge of CS
will reset the
watchdog timer.
Principles of Operation
Power-on Reset
Application of power to the X5043, X5045 activate a Power-
on Reset Circuit. This circuit pulls the RESET
/RESET pin
active. RESET
/RESET prevents the system microprocessor
from starting to operate with insufficient voltage or prior to
stabilization of the oscillator. When V
CC
exceeds the device
V
TRIP
value for 200ms (nominal) the circuit releases
RESET
/RESET, allowing the processor to begin executing
code.
Low Voltage Monitoring
During operation, the X5043, X5045 monitor the V
CC
level
and asserts RESET
/RESET if supply voltage falls below a
preset minimum V
TRIP
. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET
/RESET signal remains
active until the voltage drops below 1V. It also remains active
until V
CC
returns and exceeds V
TRIP
for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS
/WDI pin periodically to prevent an active
RESET
/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the Status Register determines the watchdog timer period.
The microprocessor can change these watchdog bits. With
8 Ld SOIC/PDIP/MSOP
CS
/WDI
WP
SO
1
2
3
4
RESET
/RESET
8
7
6
5
V
CC
X5043, X5045
V
SS
SCK
SI
14 Ld TSSOP
CS
NC
SO
1
2
3
4
RESET
/RESET
14
13
12
11
V
CC
X5043, X5045
NC
NC
NC
WP
NC
5
6
7
V
SS
NC
10
9
8
SCK
SI
Pin Names
SYMBOL DESCRIPTION
CS
/WDI Chip Select Input
SO Serial Output
SI Serial Input
SCK Serial Clock Input
WP Write Protect Input
V
SS
Ground
V
CC
Supply Voltage
RESET
/RESET Reset Output
X5043, X5045
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