TI-DIX4192-Q1：汽车级数字音频接口接收器与发射器

需积分: 5 68 浏览量更新于2024-06-28 4 收藏 924KB PDF 举报

"TI-DIX4192-Q1.pdf 是一款由德州仪器（Texas Instruments）推出的汽车级数字音频接口接收器和发射器芯片，适用于车载娱乐系统中的音频处理。" TI-DIX4192-Q1是专为汽车应用设计的集成电路，符合AEC-Q100标准，确保其在极端温度条件下的可靠性和稳定性。该器件分为两个温度等级：DIX4192I-Q1适用于第三级温度范围（-40°C to +85°C），而DIX4192T-Q1适用于第二级温度范围（-40°C to +105°C），这使得该芯片能够在各种严苛的汽车环境中正常工作。这款芯片集成了数字音频接口发射器（Digital Audio Interface Transmitter, DIT），能够将PCM（脉冲编码调制）/编码数据转换为S/PDIF（同轴数字音频接口）信号。它支持高达216kHz的采样率，保证了高质量的音频传输。此外，DIX4192-Q1还包含一个差分线路驱动器和CMOS缓冲器，以增强信号的传输性能和抗干扰能力。该器件还具备多种接口，如S/PDIF输入和输出、S/PDIF发送（TX）和接收（RX）、I2S/PCM以及I2S/PCM/TDM（时间分复用），满足不同音频设备间的通信需求。I2C接口则用于配置和控制芯片的各项功能。此外，TI-DIX4192-Q1还包括一个Line/Mic输入的ADC（模拟到数字转换器），如PCM1864-Q1，可以处理麦克风或线路输入的模拟音频信号。这个解决方案非常适合于车载娱乐系统的“Head Unit”（头部单元），如汽车音响系统，以及可能包含的外部天线放大器。通过这些接口和功能，DIX4192-Q1能够处理从不同音频源接收的信号，并将其转换为适合车载音响系统播放的格式，同时提供与其它汽车电子设备的兼容性。 TI-DIX4192-Q1是汽车音频系统设计中的一款关键组件，它提供了高精度的音频信号处理能力，适应广泛的环境条件，并具备丰富的接口选项，确保了汽车内部音频系统的高效运作和高品质声音体验。

DIR_OUT

PORT_A_IN

PORT_B_IN

Audio Serial

Port A

Audio Serial

Port B

Digital

Interface

Receiver (DIR)

Digital

Interface

Transmitter

(DIT)

TX+

TX-

SDINA

SDOUTA

LRCKA

BCKA

SDINB

SDOUTB

LRCKB

BCKB

CPM

CS or A0

CCLK or SCL

CDIN or A1

CDOUT or SDA

INT

RST

Host

Interface

(SPI or I C)

and

General-

Purpose

Outputs

Master

Clock

Distribution

MCLK

RXCKI

From RXCKO

GPO1

GPO2

GPO3

GPO4

AESOUT

RXCKO

LOCK

RX2+

RX2-

RX3+

RX3-

RX4+

RX4-

RX1+

RX1-

BLS

SYNC

Control and Status

Registers

DIR C and U

Data Buffers

DIT C and U

Data Buffers

TI Device

Power

VDD18

DGND1

VDD33

DGND2

VIO

DGND3

VCC

AGND

BGND

Internally Tied

to Substrate

PORT A

PORT B

DIR

DIT

DIX4192-Q1

SBFS041A –JULY 2016–REVISED APRIL 2017

www.ti.com

Product Folder Links: DIX4192-Q1

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 RESET Operation

The DIX4192-Q1 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize

the internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The

reset low pulse duration must be a minimum of 500 ns in length. The user must not attempt a write or read

operation using either the SPI or I

C port for at least 500 μs after the rising edge of RST. See Figure 6 for the

reset timing sequence of the DIX4192 -Q1.

In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby

all registers and buffers are forced to their default settings. Refer to Control Registers for details regarding the

RESET bit function.

Upon reset initialization, all functional blocks of the DIX4192-Q1 default to the power-down state, with the

exception of the SPI or I

C host interface and the corresponding control registers. The user may then program

the DIX4192-Q1 to the desired configuration, and release the desired function blocks from the power-down state

using the corresponding bits in control register 0x01.

RST

500ns (min)

500 sm (min)

Write orRead

via

S IorP I C

DIX4192-Q1

www.ti.com

SBFS041A –JULY 2016–REVISED APRIL 2017

Product Folder Links: DIX4192-Q1

Feature Description (continued)

Figure 6. Reset Sequence Timing

9.3.2 Master and Reference Clocks

The DIX4192-Q1 includes two clock inputs, MCLK (pin 25) and RXCKI (pin 13). The MCLK clock input is typically

used as the master clock source for the audio serial ports and/or the DIT. The MCLK may also be used as the

reference clock for the DIR. The RXCKI clock input is typically used for the DIR reference clock source, although

it may also be used as the master or reference clock source for the audio serial ports.

In addition to the MCLK and RXCKI clock sources, the DIR core recovers a master clock from the AES3-

encoded input data stream. This clock is suitable for use as a master or system clock source in many

applications. The recovered master clock output, RXCKO (pin 12), may be used as the master or reference clock

source for the audio serial ports and the DIT, as well as external audio devices.

The master clock frequency for the audio serial ports (Port A and Port B) depends on the Slave or Master mode

configuration of the port. In Slave mode, the ports do not require a master clock because the left/right word and

bit clocks are inputs, sourced from an external audio device serving as the serial bus timing master. In Master

mode, the serial ports derive the left/right word and bit clock outputs from the selected master clock source,

MCLK, RXCKI, or RXCKO. The left/right word clock rate is derived from the selected master clock source using

one of four clock divider settings (divide by 128, 256, 384, or 512). Refer to Audio Serial Port Operation for

additional details.

The DIT always requires a master clock source, which may be either the MCLK input, or the DIR recovered clock

output, RXCKO. Like the audio serial ports, the DIT output frame rate is derived from the selected master clock

using one of four clock divider settings (divide-by-128, -256, -384, or -512). Refer to Digital Interface Transmitter

(DIT) Operation for additional details.

The DIR reference clock may be any frequency that meets the PLL1 set-up requirements, described in Control

Registers. Typically, a common audio system clock rate, such as 11.2896 MHz, 12.288 MHz, 22.5792 MHz, or

24.576 MHz, may be used for this clock.

TI recommends that the clock sources for MCLK and RXCKI input be generated by low-jitter crystal oscillators for

optimal performance. In general, phase-locked loop (PLL) clock synthesizers must be avoided, unless they are

designed or specified for low clock jitter.

Master

Clock

Source

Master

Mo ed

Clock

Generation

Serial

Input

Serial

Output

MC KL

RXCKI

RXCKO

Audio Data

InternalClocks

OUTS[1:0] MU ET F T[1:M 0]

M/S DIV1:[ 0]CLK1:[ 0]

SDNI A (pin39)or SDINB(pin4 )6

LRCKA (pin3 )or8 LRCKB( i 47)p n

BCKA(pin37)orBCKB(pin48)

SDOUTA (pin40)or SDOUTB(pin45)

Daat

Source

PortA

PortB

DIR

DIX4192-Q1

SBFS041A –JULY 2016–REVISED APRIL 2017

www.ti.com

Product Folder Links: DIX4192-Q1

Feature Description (continued)

9.3.3 Audio Serial Port Operation

The DIX4192-Q1 includes two audio serial ports, Port A and Port B. Both ports are 4-wire synchronous serial

interfaces, supporting simultaneous input and output operation. Because each port has only one pair of left or

right word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in

Figure 7.

The audio serial ports may be operated at sampling rates up to 216 kHz, and support audio data word lengths up

to 24 bits. Philips I

S, Left-Justified, and Right-Justified serial data formats are supported. Refer to Figure 8.

The left or right word clock (LRCKA or LRCKB) and the bit clock (BCKA or BCKB) may be configured for either

Master or Slave mode operation. In Master mode, these clocks are outputs, derived from the selected master

clock source using internal clock dividers. The master clock source may be 128, 256, 384, or 512 times the audio

input/output sampling rate, with the clock divider being selected using control register bits for each port. In Slave

mode the left or right word and bit clocks are inputs, and are sourced from an external audio device acting as the

serial bus master.

The LRCKA or LRCKB clocks operate at the input and output sampling rate, f

. The BCKA and BCKB clock rates

are fixed at 64 times the left or right word clock rate in Master mode. For Slave mode, the minimum BCKA and

BCKB clock rate is determined by the audio data word length multiplied by two, because there are two audio

data channels per left or right word clock period. For example, if the audio data word length is 24 bits, the bit

clock rate must be at least 48 times the left or right word clock rate, allowing one bit clock period for each data bit

in the serial bit stream.

Serial audio data is clocked into the port on the rising edge of the bit clock, while data is clocked out of the port

on the falling edge of the bit clock. Refer to the Audio Serial Ports section of the Electrical Characteristics table

for parametric information and Figure 1 for a timing diagram related to audio serial port operation.

The audio serial ports are configured using control registers 0x03 through 0x06. Refer to Control Registers for

descriptions of the control register bits.

Figure 7. Audio Serial Port Block Diagram

剩余66页未读，继续阅读

不觉明了

粉丝: 3983
资源: 5759

TI-DIX4192-Q1：汽车级数字音频接口接收器与发射器

TI-DIX4192.pdf

TI-DIT4192.pdf

TI-DIX9211.pdf

04-Human-Computer-Interaction-3rd-Edition-by-ALAN-DIX-JANET-FINLAY-ISBN-0130461091-pdf.zip

Microservice-Architecture-Aligning-Principles-Practices-and-Culture.pdf

Addison.Wesley.Service-Oriented.Design.with.Ruby.and.Rails

Python库 | lexc2dix-1.0-py2.py3-none-any.whl

TI-PCM9211.pdf

Paul-Dix--Thundergod:放心部署

以太网标准解析：DIX V2与IEEE 802.3的差异与功能

最新资源