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QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 0
xx NXP Semiconductors
Contents
Paragraph
Number Title
Page
Number
5.5.5.6 BMI Tx Flow—Independent Mode ..................................................................... 5-216
5.5.5.7 BMI Offline Port Flow ........................................................................................ 5-216
5.5.5.7.1 Initialization..................................................................................................... 5-216
5.5.5.7.2 Offline BMI ‘Allocate internal IC’ and QMI dequeue.................................... 5-216
5.5.5.7.3 BMI Offline ‘frame fetch’ ............................................................................... 5-217
5.5.5.7.4 BMI Offline ‘Discard Frame’ or ‘Prepare to Enqueue Frame’ ....................... 5-218
5.5.5.7.5 BMI Offline ‘Release Internal Buffers’........................................................... 5-219
5.5.5.7.6 Illegal combinations ........................................................................................ 5-219
5.5.5.8 BMI Host Command Flow .................................................................................. 5-220
5.5.6 BMI Internal Operation Details ............................................................................... 5-220
5.5.6.1 Operational Mode bits ......................................................................................... 5-220
5.5.6.2 Buffer Pool Selection for Rx and O/H................................................................. 5-221
5.5.6.2.1 Backup Pools ................................................................................................... 5-221
5.5.6.3 Restrictions on a scatter/gather list ...................................................................... 5-221
5.5.6.4 Internal and External Margins ............................................................................. 5-222
5.5.6.4.1 Internal Margins............................................................................................... 5-222
5.5.6.4.2 External Margins ............................................................................................. 5-222
5.5.6.4.3 External memory accesses optimization.......................................................... 5-224
5.5.6.5 Conditions that enable Tx checksum generation ................................................. 5-224
5.5.6.6 Conditions that enable Offline checksum validation........................................... 5-225
5.5.6.7 Transmit Confirmation Type (TXCT) ................................................................. 5-225
5.5.6.8 Rx Normal mode and Offline - Enqueue or discard decision logic..................... 5-226
5.5.6.9 Tx confirmation enqueue and buffer deallocation decision................................. 5-228
5.5.6.10 Offline Port Enqueue Decision Flow................................................................... 5-231
5.5.6.11 Host command enqueue decision flow ................................................................ 5-232
5.5.6.12 DMA resource Load balancing............................................................................ 5-232
5.5.6.13 FMan DMA Priority Elevation............................................................................ 5-233
5.5.6.14 ICID (Isolation Context Identifier)...................................................................... 5-233
5.5.6.15 Congestion or Rejection Handling....................................................................... 5-234
5.5.6.16 Pause Frames for Flow Control ........................................................................... 5-234
5.5.6.17 Tx and O/H Rate Limiter..................................................................................... 5-235
5.5.6.18 Internal FIFO Configuration Requirements......................................................... 5-236
5.5.6.18.1 Internal FIFO for Rx Ports............................................................................... 5-236
5.5.6.18.2 Internal FIFO for Tx Ports............................................................................... 5-237
5.5.6.18.3 Internal FIFO for O/H Ports ............................................................................ 5-237
5.5.6.19 Hardware Assist for IEEE 1588-Compliant Timestamping ................................ 5-237
5.5.6.20 Error Handling ..................................................................................................... 5-238
5.5.6.20.1 Non-Recoverable Errors .................................................................................. 5-238
5.5.6.20.2 Network Errors ................................................................................................ 5-238
5.5.6.20.3 Buffer Depletion .............................................................................................. 5-239
5.5.6.20.4 Queue Error ..................................................................................................... 5-239