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首页QorIQ LS1043A DPAA 参考手册:加速架构详解
"QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual"
这篇文档是关于NXP公司的QorIQ LS1043A处理器的数据路径加速架构(DPAA)的参考手册,主要适用于LS1023A、LS1043A系列芯片。该手册发布于2016年4月,版本号为Rev.0。NXP是一家知名的半导体公司,其产品广泛应用于网关和5G通信等领域。
DPAA是NXP设计的一种高级架构,旨在提升数据处理速度和效率,特别适合网络和存储应用。它通过集成特定的硬件加速器和智能网络接口,能够高效地处理数据包,降低了CPU的负载,提升了系统的整体性能。
在LS1043A处理器中,DPAA可能包括以下关键组件:
1. **FlexBuffer**:这是一个灵活的缓冲区管理机制,用于在数据包处理过程中提供高效的数据存储和传输。它支持动态调整缓冲区大小,以适应不同工作负载的需求。
2. **FlexEngine**:这是DPAA的核心部分,它包含一组可编程的硬件引擎,专门设计用于执行网络协议处理和数据包处理任务,如TCP/IP协议栈卸载、报文分类和流量控制。
3. **Network Controllers**:如以太网控制器,它们提供了高速的网络连接,支持多个端口,可以处理多种协议,如Ethernet、TCP/IP等。
4. **Security Engines**:这些硬件加速器用于加密和解密数据,支持常见的安全协议,如IPsec、TLS,确保数据传输的安全性。
5. **DMA(Direct Memory Access)Controllers**:DMA控制器允许数据在不经过CPU的情况下直接在内存和外设之间传输,提高了数据吞吐量。
6. **Multi-core Synchronization**:由于LS1043A是一款多核处理器,DPAA还包括了核心间的同步机制,确保多核之间的协同工作和一致性。
7. **Management Engine**:负责监控和管理系统资源,如错误检测、调试和维护功能。
8. **Software Stack Support**:DPAA通常与特定的软件栈一起工作,包括设备驱动程序、中间件和应用程序接口(API),以简化开发过程并提供高级功能。
在实际应用中,开发者可以利用DPAA的优势来构建高性能的网络设备,如路由器、交换机、安全网关和5G通信基础设施。手册详细介绍了这些组件的使用方法、配置选项以及编程接口,为开发者提供了全面的技术指导。
请注意,文档中还强调,提供的信息仅用于帮助系统和软件实现者使用NXP产品,但并不授予任何版权许可。NXP对其产品的适用性不做任何明示或暗示的保证,并且不对任何产品或电路的应用或使用承担任何责任。此外,典型参数可能会因应用而异,实际性能可能会随时间变化。因此,开发者应根据具体应用需求仔细评估和测试。
QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 0
xvi NXP Semiconductors
Contents
Paragraph
Number Title
Page
Number
5.5.2 Frame Manager BMI Overview................................................................................. 5-75
5.5.2.1 Frame Manager BMI Features.............................................................................. 5-75
5.5.2.2 Frame Manager BMI Modes of Operation ............................................................ 5-78
5.5.3 BMI Input NIA .......................................................................................................... 5-78
5.5.4 Frame Manager BMI Memory Map and Register Definition.................................... 5-80
5.5.4.1 Storage Profiles...................................................................................................... 5-87
5.5.4.1.1 Storage Profile Virtualization per port (for Rx and Offline ports) .................... 5-88
5.5.4.1.2 Hardware port storage profiles .......................................................................... 5-89
5.5.4.1.3 Virtual storage profiles ...................................................................................... 5-90
5.5.4.2 Congestion Group Priority Mapping table ............................................................ 5-93
5.5.4.3 PFC priority mapping to QMan traffic classes ...................................................... 5-93
5.5.4.4 FMan BMI Common Registers Description.......................................................... 5-93
5.5.4.4.1 BMI Initialization Register (FMBM_INIT) ...................................................... 5-93
5.5.4.4.2 BMI Configuration 1 Register (FMBM_CFG1) ............................................... 5-94
5.5.4.4.3 BMI Configuration 2 Register (FMBM_CFG2) ............................................... 5-96
5.5.4.4.4 Interrupt Event Register (FMBM_IEVR).......................................................... 5-96
5.5.4.4.5 Interrupt Enable Register (FMBM_IER)........................................................... 5-97
5.5.4.4.6 Interrupt Force Register (FMBM_IFR)............................................................. 5-98
5.5.4.4.7 Debug Trap Counter Register (FMBM_DTC) ................................................. 5-99
5.5.4.4.8 Debug Compare Value Register (FMBM_DCV) .............................................. 5-99
5.5.4.4.9 Debug Compare Mask (FMBM_DCM) .......................................................... 5-100
5.5.4.4.10 Global Debug Enable (FMBM_GDE)............................................................. 5-100
5.5.4.4.11 Port Parameters Register (FMBM_PP_1–63) ................................................. 5-101
5.5.4.4.12 Port FIFO Size Register (FMBM_PFS_1–63) ................................................ 5-103
5.5.4.4.13 SPICID Register (FMBM_SPICID_1–63)...................................................... 5-106
5.5.4.5 Rx Port Register Descriptions ............................................................................. 5-108
5.5.4.5.1 Rx Configuration Register (FMBM_RCFG)................................................... 5-108
5.5.4.5.2 Rx Status Register (FMBM_RST)................................................................... 5-109
5.5.4.5.3 Rx DMA Attributes Register (FMBM_RDA)................................................. 5-110
5.5.4.5.4 Rx FIFO Parameters Register (FMBM_RFP) ................................................. 5-112
5.5.4.5.5 Rx Frame End Data Register (FMBM_RFED) ............................................... 5-113
5.5.4.5.6 Rx Internal Context Parameters (FMBM_RICP) ............................................ 5-115
5.5.4.5.7 Rx Internal Margins Register (FMBM_RIM) ................................................. 5-116
5.5.4.5.8 Rx External Buffer Margins Register (FMBM_REBM) ................................. 5-117
5.5.4.5.9 Rx Frame Next Engine Register (FMBM_RFNE) .......................................... 5-118
5.5.4.5.10 Rx Frame Attributes Register (FMBM_RFCA).............................................. 5-119
5.5.4.5.11 Rx Frame Parser Next Engine Register (FMBM_RFPNE)............................. 5-120
5.5.4.5.12 Rx Parsing Start Offset Register (FMBM_RPSO) .......................................... 5-121
5.5.4.5.13 Rx Policer Profile Register (FMBM_RPP) ..................................................... 5-121
5.5.4.5.14 Rx Parse Result Initialization Register (FMBM_RPRI) ................................. 5-122
5.5.4.5.15 Rx Frame Queue ID Register (FMBM_RFQID)............................................. 5-123
QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 0
NXP Semiconductors xvii
Contents
Paragraph
Number Title
Page
Number
5.5.4.5.16 Rx Error Frame Queue ID Register (FMBM_REFQID)................................. 5-124
5.5.4.5.17 Rx Frame Status Discard Mask Register (FMBM_RFSDM).......................... 5-125
5.5.4.5.18 Rx Frame Status Error Mask Register (FMBM_RFSEM) .............................. 5-125
5.5.4.5.19 Rx Frame Enqueue Next Engine Register (FMBM_RFENE)......................... 5-126
5.5.4.5.20 Rx Continuous Mode Next Enqueue Register (FMBM_RCMNE)................. 5-127
5.5.4.5.21 Rx External Buffers Manager Pool Information Register (FMBM_REBMPI).........
5-127
5.5.4.5.22 Rx Allocate Counter Register (FMBM_RACNT)........................................... 5-129
5.5.4.5.23 Receive Congestion Group Map Register (FMBM_RCGM).......................... 5-130
5.5.4.5.24 BMan Pool Depletion Register (FMBM_RMPD)........................................... 5-131
5.5.4.5.25 Statistics Counters Register (FMBM_RSTC) ................................................. 5-132
5.5.4.5.26 Rx Frame Counter Register (FMBM_RFRC) ................................................. 5-133
5.5.4.5.27 Rx Bad Frames Counter Register (FMBM_RBFC) ........................................ 5-133
5.5.4.5.28 Rx Large Frames Counter Register (FMBM_RLFC)...................................... 5-134
5.5.4.5.29 Rx Filter Frames Counter Register (FMBM_RFFC) ...................................... 5-135
5.5.4.5.30 Rx Frames Discard Counter Register (FMBM_RFDC) .................................. 5-135
5.5.4.5.31 Rx Frames List DMA Error Counter Register (FMBM_RFLDEC)................ 5-136
5.5.4.5.32 Rx Out of Buffers Discard Counter Register (FMBM_RODC)...................... 5-137
5.5.4.5.33 Rx Buffers Deallocate Counter Register (FMBM_RBDC)............................. 5-138
5.5.4.5.34 RX Prepare to Enqueue Counter (FMBM_RPEC).......................................... 5-138
5.5.4.5.35 Rx Performance Counters Register (FMBM_RPC) ........................................ 5-139
5.5.4.5.36 Rx Performance Count Parameters Register (FMBM_RPCP)........................ 5-139
5.5.4.5.37 Rx Cycle Counter Register (FMBM_RCCN) ................................................. 5-141
5.5.4.5.38 Rx Tasks Utilization Counter Register (FMBM_RTUC) ................................ 5-142
5.5.4.5.39 Rx Receive Queue Utilization Counter Register (FMBM_RRQUC) ............. 5-142
5.5.4.5.40 Rx DMA Utilization Counter Register (FMBM_RDUC) ............................... 5-143
5.5.4.5.41 Rx FIFO Utilization Counter Register (FMBM_RFUC) ................................ 5-144
5.5.4.5.42 Rx Pause Activation Counter Register (FMBM_RPAC) ................................ 5-144
5.5.4.5.43 Rx Debug Configuration Register (FMBM_RDCFG) .................................... 5-145
5.5.4.5.44 Rx General Purpose Register (FMBM_RGPR)............................................... 5-147
5.5.4.6 Tx Port Register Descriptions.............................................................................. 5-147
5.5.4.6.1 Tx Configuration Register (FMBM_TCFG) ................................................... 5-147
5.5.4.6.2 Tx Status Register (FMBM_TST) ................................................................... 5-148
5.5.4.6.3 Tx DMA Attributes Register (FMBM_TDA) ................................................. 5-149
5.5.4.6.4 Tx FIFO Parameters Register (FMBM_TFP) ................................................. 5-149
5.5.4.6.5 Tx Frame End Data Register (FMBM_TFED)................................................ 5-151
5.5.4.6.6 Tx Internal Context Parameters Register (FMBM_TICP) .............................. 5-152
5.5.4.6.7 Tx Frame Dequeue Next Engine Register (FMBM_TFDNE) ........................ 5-153
5.5.4.6.8 Tx Frame Attributes Register (FMBM_TFCA) .............................................. 5-154
5.5.4.6.9 Tx Confirmation Frame Queue ID Register (FMBM_TCFQID).................... 5-155
5.5.4.6.10 Tx Error Frame Queue ID Register (FMBM_TEFQID) ................................. 5-156
QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 0
xviii NXP Semiconductors
Contents
Paragraph
Number Title
Page
Number
5.5.4.6.11 Tx Frame Enqueue Next Engine Register (FMBM_TFENE) ......................... 5-156
5.5.4.6.12 Tx Rate Limiter Scale Register (FMBM_TRLMTS) ...................................... 5-157
5.5.4.6.13 Tx Rate Limiter Register (FMBM_TRLMT).................................................. 5-158
5.5.4.6.14 Tx Custom Classifier Base Register (FMBM_TCCB).................................... 5-159
5.5.4.6.15 Tx Frame Next Engine Register (FMBM_TFNE) .......................................... 5-160
5.5.4.6.16 Tx Priority based Flow Control (PFC) Mapping Registers (FMBM_TPFCM0) ......
5-160
5.5.4.6.17 Tx Continuous Mode Next Enqueue Register (FMBM_TCMNE) ................. 5-161
5.5.4.6.18 Tx Statistics Counters Register (FMBM_TSTC) ............................................ 5-162
5.5.4.6.19 Tx Frame Counter Register (FMBM_TFRC).................................................. 5-163
5.5.4.6.20 Tx Frames Discard Counter Register (FMBM_TFDC) .................................. 5-163
5.5.4.6.21 Tx Frames Length Error Discard Counter Register (FMBM_TFLEDC)........ 5-164
5.5.4.6.22 Tx Frames Unsupported Format Discard Counter Register (FMBM_TFUFDC) .....
5-165
5.5.4.6.23 Tx Buffers Deallocate Counter Register (FMBM_TBDC) ............................. 5-165
5.5.4.6.24 Tx Performance Counters Register (FMBM_TPC)......................................... 5-166
5.5.4.6.25 Tx Performance Count Parameters Register (FMBM_TPCP) ........................ 5-166
5.5.4.6.26 Tx Cycle Counter Register (FMBM_TCCN).................................................. 5-168
5.5.4.6.27 Tx Tasks Utilization Counter Register (FMBM_TTUC) ................................ 5-169
5.5.4.6.28 Tx Transmit Confirm Queue Utilization Counter Register (FMBM_TTCQUC) .....
5-169
5.5.4.6.29 Tx DMA Utilization Counter Register (FMBM_TDUC)................................ 5-170
5.5.4.6.30 Tx FIFO Utilization Counter Register (FMBM_TFUC)................................. 5-171
5.5.4.6.31 Tx Debug Configuration Register (FMBM_TDCFG)..................................... 5-171
5.5.4.6.32 Tx General Purpose Register (FMBM_TGPR) ............................................... 5-173
5.5.4.7 Offline Port/Host Command Port Registers Description..................................... 5-174
5.5.4.7.1 Offline Port/Host Command (O/H) Configuration Register (FMBM_OCFG)5-174
5.5.4.7.2 O/H Status Register (FMBM_OST) ................................................................ 5-175
5.5.4.7.3 O/H DMA Attributes Register (FMBM_ODA) .............................................. 5-176
5.5.4.7.4 O/H Internal Context Parameters Register (FMBM_OICP) ........................... 5-177
5.5.4.7.5 O/H Frame Dequeue Next Engine Register (FMBM_OFDNE) ..................... 5-179
5.5.4.7.6 O/H Frame Next Engine Register (FMBM_OFNE)........................................ 5-179
5.5.4.7.7 O/H Frame Attributes Register (FMBM_OFCA) ........................................... 5-180
5.5.4.7.8 O/H Frame Parser Next Engine Register (FMBM_OFPNE) .......................... 5-181
5.5.4.7.9 O/H Parsing Start Offset Register (FMBM_OPSO)........................................ 5-182
5.5.4.7.10 O/H Policer Profile Register (FMBM_OPP)................................................... 5-182
5.5.4.7.11 O/H Custom Classifier Base Register (FMBM_OCCB)................................. 5-183
5.5.4.7.12 O/H Internal Margins Register (FMBM_OIM)............................................... 5-183
5.5.4.7.13 O/H FIFO Parameters Register (FMBM_OFP)............................................... 5-184
5.5.4.7.14 O/H Frame End Data Register (FMBM_OFED)............................................. 5-185
5.5.4.7.15 O/H Parse Result Initialization Register (FMBM_OPRI)............................... 5-186
QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 0
NXP Semiconductors xix
Contents
Paragraph
Number Title
Page
Number
5.5.4.7.16 O/H Frame Queue ID Register (FMBM_OFQID) .......................................... 5-187
5.5.4.7.17 O/H Error Frame Queue ID Register (FMBM_OEFQID) .............................. 5-188
5.5.4.7.18 O/H Frame Status Discard Mask Register (FMBM_OFSDM) ....................... 5-189
5.5.4.7.19 O/H Frame Status Error Mask Register (FMBM_OFSEM)............................ 5-189
5.5.4.7.20 O/H Frame Enqueue Next Engine Register (FMBM_OFENE) ...................... 5-190
5.5.4.7.21 O/H Rate Limiter Scale Register (FMBM_ORLMTS) ................................... 5-191
5.5.4.7.22 O/H Rate Limiter Register (FMBM_ORLMT) ............................................... 5-192
5.5.4.7.23 O/H Continuous Mode Next Enqueue Register (FMBM_OCMNE) .............. 5-193
5.5.4.7.24 FMBM_OCGM - Observed Congestion Group Map...................................... 5-194
5.5.4.7.25 O/H Statistics Counters Register (FMBM_OSTC) ......................................... 5-195
5.5.4.7.26 O/H Frame Counter Register (FMBM_OFRC)............................................... 5-196
5.5.4.7.27 O/H Frames Discard Counter Register (FMBM_OFDC)................................ 5-196
5.5.4.7.28 O/H Frames Length Error Discard Counter Register (FMBM_OFLEDC)..... 5-197
5.5.4.7.29 O/H Frames Unsupported Format Discard Counter Register (FMBM_OFUFDC) ..
5-198
5.5.4.7.30 O/H Filter Frames Counter Register (FMBM_OFFC) .................................... 5-198
5.5.4.7.31 O/H Frames WRED Discard Counter Register (FMBM_OFWDC) ............... 5-199
5.5.4.7.32 O/H Frames List DMA Error Counter Register (FMBM_OFLDEC) ............. 5-200
5.5.4.7.33 O/H Buffers Deallocate Counter Register (FMBM_OBDC) .......................... 5-201
5.5.4.7.34 O/H Out of Buffers Discard Counter Register (FMBM_OODC) ................... 5-201
5.5.4.7.35 O/H Prepare to Enqueue Counter (FMBM_OPEC) ........................................ 5-202
5.5.4.7.36 O/H Performance Counters Register (FMBM_OPC)...................................... 5-203
5.5.4.7.37 O/H Performance Count Parameters Register (FMBM_OPCP) ..................... 5-203
5.5.4.7.38 O/H Cycle Counter Register (FMBM_OCCN) ............................................... 5-205
5.5.4.7.39 O/H Tasks Utilization Counter Register (FMBM_OTUC) ............................. 5-205
5.5.4.7.40 O/H DMA Utilization Counter Register (FMBM_ODUC)............................. 5-206
5.5.4.7.41 O/H FIFO Utilization Counter Register (FMBM_OFUC) .............................. 5-207
5.5.4.7.42 O/H Debug Configuration Register (FMBM_ODCFG).................................. 5-207
5.5.4.7.43 O/H General Purpose Register (FMBM_OGPR) ............................................ 5-209
5.5.5 Frame Manager BMI Functional Description.......................................................... 5-209
5.5.5.1 Introduction to BMI Functional Description ....................................................... 5-209
5.5.5.2 Introduction to BMI Data flows .......................................................................... 5-210
5.5.5.3 BMI Rx Flow—Normal Mode ............................................................................ 5-211
5.5.5.3.1 Initialization..................................................................................................... 5-211
5.5.5.3.2 BMI ‘Rx Frame’ .............................................................................................. 5-212
5.5.5.3.3 Rx BMI ‘Discard Frame’ or ‘Prepare to Enqueue Frame’ .............................. 5-212
5.5.5.3.4 BMI ‘Release Internal Buffers’ ....................................................................... 5-213
5.5.5.4 BMI Rx Flow—Independent Mode..................................................................... 5-214
5.5.5.5 BMI Tx Flow—Normal Mode............................................................................ 5-214
5.5.5.5.1 Tx BMI ‘Allocate internal IC’ and QMI dequeue........................................... 5-214
5.5.5.5.2 BMI ‘Transmit Frame’ or ‘Process and Transmit Frame’ ............................... 5-215
QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 0
xx NXP Semiconductors
Contents
Paragraph
Number Title
Page
Number
5.5.5.6 BMI Tx Flow—Independent Mode ..................................................................... 5-216
5.5.5.7 BMI Offline Port Flow ........................................................................................ 5-216
5.5.5.7.1 Initialization..................................................................................................... 5-216
5.5.5.7.2 Offline BMI ‘Allocate internal IC’ and QMI dequeue.................................... 5-216
5.5.5.7.3 BMI Offline ‘frame fetch’ ............................................................................... 5-217
5.5.5.7.4 BMI Offline ‘Discard Frame’ or ‘Prepare to Enqueue Frame’ ....................... 5-218
5.5.5.7.5 BMI Offline ‘Release Internal Buffers’........................................................... 5-219
5.5.5.7.6 Illegal combinations ........................................................................................ 5-219
5.5.5.8 BMI Host Command Flow .................................................................................. 5-220
5.5.6 BMI Internal Operation Details ............................................................................... 5-220
5.5.6.1 Operational Mode bits ......................................................................................... 5-220
5.5.6.2 Buffer Pool Selection for Rx and O/H................................................................. 5-221
5.5.6.2.1 Backup Pools ................................................................................................... 5-221
5.5.6.3 Restrictions on a scatter/gather list ...................................................................... 5-221
5.5.6.4 Internal and External Margins ............................................................................. 5-222
5.5.6.4.1 Internal Margins............................................................................................... 5-222
5.5.6.4.2 External Margins ............................................................................................. 5-222
5.5.6.4.3 External memory accesses optimization.......................................................... 5-224
5.5.6.5 Conditions that enable Tx checksum generation ................................................. 5-224
5.5.6.6 Conditions that enable Offline checksum validation........................................... 5-225
5.5.6.7 Transmit Confirmation Type (TXCT) ................................................................. 5-225
5.5.6.8 Rx Normal mode and Offline - Enqueue or discard decision logic..................... 5-226
5.5.6.9 Tx confirmation enqueue and buffer deallocation decision................................. 5-228
5.5.6.10 Offline Port Enqueue Decision Flow................................................................... 5-231
5.5.6.11 Host command enqueue decision flow ................................................................ 5-232
5.5.6.12 DMA resource Load balancing............................................................................ 5-232
5.5.6.13 FMan DMA Priority Elevation............................................................................ 5-233
5.5.6.14 ICID (Isolation Context Identifier)...................................................................... 5-233
5.5.6.15 Congestion or Rejection Handling....................................................................... 5-234
5.5.6.16 Pause Frames for Flow Control ........................................................................... 5-234
5.5.6.17 Tx and O/H Rate Limiter..................................................................................... 5-235
5.5.6.18 Internal FIFO Configuration Requirements......................................................... 5-236
5.5.6.18.1 Internal FIFO for Rx Ports............................................................................... 5-236
5.5.6.18.2 Internal FIFO for Tx Ports............................................................................... 5-237
5.5.6.18.3 Internal FIFO for O/H Ports ............................................................................ 5-237
5.5.6.19 Hardware Assist for IEEE 1588-Compliant Timestamping ................................ 5-237
5.5.6.20 Error Handling ..................................................................................................... 5-238
5.5.6.20.1 Non-Recoverable Errors .................................................................................. 5-238
5.5.6.20.2 Network Errors ................................................................................................ 5-238
5.5.6.20.3 Buffer Depletion .............................................................................................. 5-239
5.5.6.20.4 Queue Error ..................................................................................................... 5-239
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