Microchip KS9131: 高集成千兆以太网PHY芯片

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"KS9131是一款由Microchip Technology Inc.推出的高性能网络接收PHY芯片，适用于10Base-T、100Base-TX和1000Base-T的IEEE 802.3标准，支持通过CAT 5 UTP和CAT 3 UTP电缆进行数据传输。该芯片集成了多种功能，包括自动协商、线路终端电阻、低功耗模式以及能源高效以太网支持等。此外，它还提供了醒目的LED控制、线缆诊断和信号质量指示等功能。" KS9131是Microchip Technology公司设计的一款高度集成的以太网PHY收发器，旨在满足各种IEEE 802.3应用的需求。此芯片具备以下关键特性： 1. **单片10/100/1000Mbps以太网收发器**：KS9131支持10 Mbps、100 Mbps和1000 Mbps的传输速度，可适应不同网络环境的需求。 2. **GMII/MII接口**：提供与3.3V/2.5V/1.8V兼容的接口，确保与不同电压等级的系统无缝对接。 3. **自动协商功能**：自动识别并选择最高连接速度（10/100/1000Mbps）和双工模式（半双工/全双工），简化了网络配置。 4. **线路终端电阻**：内部集成的差分对终端电阻，提高了信号完整性和传输效率。 5. **内置LDO控制器**：支持单一3.3V电源操作，降低了系统的复杂性。 6. **Jumbo帧支持**：最大可支持16KB的帧大小，适用于大数据传输。 7. **125MHz参考时钟输出**：提供高速时钟信号，保证数据传输的精度。 8. **节能模式**：能量检测电源下降模式在无电缆连接时降低功耗，提高能效。 9. **能源高效以太网（EEE）支持**：包含低功耗空闲（LPI）模式和100BASE-TX/1000BASE-T时钟可停止，以及10BASE-T的发射幅度减小选项。 10. **唤醒-on-LAN（WOL）**：具有强大的自定义包检测功能，允许设备在休眠状态下被网络活动唤醒。 11. **可编程LED输出**：可根据需要设置链接状态、活动和速度的LED显示。 12. **基线漂移校正**：改善了信号质量，减少了由于电缆长度变化引起的信号失真。 13. **Quiet-WIRE EMR减少**：针对100BASE-TX提供电磁干扰（EMI）降低技术。 14. **LinkMD线缆诊断**：基于TDR的诊断工具，可以检测铜缆故障，确保网络连接的可靠性。 15. **信号质量指示**：提供信号质量信息，帮助监控网络性能。 16. **参数化NAND树支持**：用于检测系统中的故障，增强了系统的稳定性。 KS9131的设计充分考虑了现代网络环境的多样性、可靠性和能效要求，使其成为各种网络设备的理想选择，如路由器、交换机、网卡和其他嵌入式网络系统。这款芯片的广泛应用得益于其全面的功能集和出色的兼容性。

KSZ9131MNX

DS00002840B-page 16  2018-2019 Microchip Technology Inc.

TABLE 3-7: I/O POWER, CORE POWER AND GROUND

Name Symbol

BUFFER

TYPE

DESCRIPTION

+2.5/3.3V

Analog Power

Supply

AVDDH P +2.5/3.3V analog power supply V

+1.2V Analog

Power Supply

AVDDL P +1.2V analog power supply V

+1.2V Analog

PLL Power

Supply

AVDDL_PLL P +1.2V analog PLL power supply V

+3.3/2.5/1.8V

Variable I/O

Power Supply

Input

DVDDH P +3.3/2.5/1.8V variable I/O digital power supply V

DD_IO

+1.2V Digital

Core Power

Supply Input

DVDDL P +1.2V digital core power supply input

Paddle Ground P_VSS GND Common ground. This exposed paddle must be connected to

the ground plane with a via array.

Analog Ground

High

AGNDH GND Analog ground high

 2018-2019 Microchip Technology Inc. DS00002840B-page 19

KSZ9131MNX

4.0 FUNCTIONAL DESCRIPTION

The KSZ9131MNX is a completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical

layer transceiver solution for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP)

cable.

The KSZ9131MNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four

differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.

On the copper media interface, the KSZ9131MNX can automatically detect and correct for differential pair misplace-

ments and polarity reversals, and correct propagation delays and re-sync timing between the four differential pairs, as

specified in the IEEE 802.3 standard for 1000BASE-T operation.

The KSZ9131MNX provides the GMII/MII interface for connection to GMACs in Gigabit Ethernet processors and

switches for data transfer at 10/100/1000Mbps.

Figure 4-1 shows a high-level block diagram of the KSZ9131MNX.

4.1 10BASE-T/100BASE-TX Transceiver

4.1.1 100BASE-TX TRANSMIT

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI con-

version, and MLT-3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial

bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized

data is further converted from NRZ-to-NRZI format, and then transmitted in MLT-3 current output. The output current is

set by an external 6.04 kΩ 1% resistor for the 1:1 transformer ratio.

The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude

balance, and overshoot. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.

4.1.2 100BASE-TX RECEIVE

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT-3-to-NRZI conversion, data

and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

FIGURE 4-1: KSZ9131MNX BLOCK DIAGRAM

MEDIA

INTERFACE

PMA

TX10/100/1000

PMA

RX1000

PMA

RX100

PMA

RX10

CLOCK

RESET

PCS10

AUTO-

NEGOTIATION

PCS100

PCS1000

INTERFACE

LED

DRIVERS

CONFIGURATIONS

GMII/MII

KSZ9131MNX

DS00002840B-page 20  2018-2019 Microchip Technology Inc.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted

pair cable. Because the amplitude loss and phase distortion are a function of the cable length, the equalizer must adjust

its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on

comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.

This is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit com-

pensates for the effect of baseline wander and improves the dynamic range. The differential data conversion circuit con-

verts the MLT-3 format back to NRZI. The slicing threshold is also adaptive.

The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then

used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/

5B decoder. Finally, the NRZ serial data is converted to the GMII/MII format and provided as the input data to the MAC.

4.1.3 SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)

The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)

and baseline wander. Transmitted data is scrambled using an 11-bit wide linear feedback shift register (LFSR). The

scrambler generates a 2047-bit non-repetitive sequence, then the receiver de-scrambles the incoming data stream

using the same sequence as at the transmitter.

4.1.4 10BASE-T TRANSMIT

The 10BASE-T output drivers are incorporated into the 100BASE-TX drivers to allow for transmission with the same

magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output signals with typical amplitude of

2.5V peak for standard 10BASE-T mode and 1.75V peak for energy-efficient 10BASE-Te mode. The 10BASE-T/

10BASE-Te signals have harmonic contents that are at least 31 dB below the fundamental frequency when driven by

an all-ones Manchester-encoded signal.

4.1.5 10BASE-T RECEIVE

On the receive side, input buffer and level-detecting squelch circuits are used. A differential input receiver circuit and a

phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock

signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths to prevent

noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks

onto the incoming signal and the KSZ9131MNX decodes a data frame. The receiver clock is maintained active during

idle periods between receiving data frames.

The KSZ9131MNX removes all 7 bytes of the preamble and presents the received frame starting with the SFD (start of

frame delimiter) to the MAC.

Auto-polarity correction is provided for the receiving differential pair to automatically swap and fix the incorrect +/– polar-

ity wiring in the cabling.

4.2 1000BASE-T Transceiver

The 1000BASE-T transceiver is based-on a mixed-signal/digital-signal processing (DSP) architecture, which includes

the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancelers, cross-talk cancelers, preci-

sion clock recovery scheme, and power-efficient line drivers.

Figure 4-2 shows a high-level block diagram of a single channel of the 1000BASE-T transceiver for one of the four dif-

ferential pairs.

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