全能硅纳米线隧道FET的电位解析电流模型

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本文主要探讨了"基于分析电位的全能栅极纳米线隧道场效应晶体管（GAA-NW-TFET）模型"。在当前先进的微电子器件发展中，GAA架构的硅纳米线隧道FET因其高集成度、低功耗特性而备受关注。作者 Ying Liu、Jin He、Mansun Chan 等来自北京大学深圳SOC实验室、PKU-HKUST深圳-香港联合机构以及香港科技大学电子与计算机工程系的研究人员合作，他们针对这一前沿技术提出了一个新颖的模型。在研发过程中，研究人员首先解决了三维泊松方程，以获取纳米线隧道FET（NW-TFET）器件在通道方向上各个分区区域的表面势分布。这个步骤对于理解电流传输机制至关重要，因为表面势决定了电子的行为和迁移效率。通过考虑带间隧穿（BTBT）效应，模型能够更精确地模拟这种复杂的量子现象。接着，作者利用Kane表达式构建了一个电流模型，该模型能够量化电荷载流子通过纳米线通道时的隧穿电流。这个模型的建立不仅考虑了传统导电机制，还包含了BTBT对电流的贡献，从而提高了模型的准确性。为了验证模型的有效性，研究者将模型预测的结果与商业化的三维技术计算机辅助设计（TCAD）模拟进行了对比。结果显示，两者之间的良好一致性表明，所提出的分析电位模型能够有效地预测GAA-NW-TFET的实际性能，这对于优化器件设计和性能预测具有重要意义。关键词：全能栅极（GAA）、纳米线隧道FET、表面势、带间隧穿、三维泊松方程、电流模型。本文的研究成果对于推动GAA-NW-TFET技术的进一步发展和实际应用具有较高的理论价值和实践指导意义。

An Analytic Potential Based Model for Gate-All-Around Nanowire Tunnel-FETs

Ying Liu

, Jin He

, Mansun Chan

, Caixia Du

***

, Yun Ye

, Wei Zhao

, Wen Wu

, and Wenping Wang

Peking University Shenzhen SOC Key Laboratory, PKU-HKUST Shenzhen-Hong Kong Institution,

Shenzhen, China

Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology,

Kowloon, Hong Kong

***

Shenzhen Huayue Teracale Chip Electronic Limited Co., Shenzhen, China

ABSTRACT

In this paper, an analytic potential based current model of

the gate-all-around (GAA) silicon nanowire tunnel-FETs

(NW-TFETs) is proposed based on the surface potential

solutions at the channel direction and considering band to

band tunneling (BTBT) efficiency. The 3-D Poisson’s

equation is solved to obtain the surface potential distribution

in the partition regions along the channel direction for

NW-TFET device and then a tunneling current model using

Kane’s expression is developed. The validity of the developed

model is proved by the good agreement between the model

predictions and TCAD simulation results.

Keywords: Gate-All-Around (GAA); nanowire tunnel-FETs

(NW-TFETs); band to band tunneling (BTBT); analytic

model.

1 INTRODUCTION

Tunnel-FETs (TFET) has been got great attention in the

semiconductor academic and industry fields in recent years

for the superior performance in sub-threshold region.

Compared with the conventional MOSFETs, TFET is

competitive and chosen due to its high ON-OFF current ratio,

below 60 mV/dec sub-threshold swing (SS) and low leakage

power consumption [1-4]. However, TFETs have a small

amount of band to band tunneling (BTBT) efficiency in the

large band gap of silicon body leading to a low ON-current.

To obtain the high ON-current and small SS, the GAA

NW-TFETs is considered as an efficient device candidate.

NW-TFET process technology and fabrication measures have

been matured recently and many research papers have been

published [4-6]. However, the compact model of NW-TFET

for circuit performance prediction and simulation has made a

few progresses. Most works only focus on NW-TFET

empirical model development [5,9]. So far, there is no a

complete analytical model of GAA NW-TFET for device

scientists and circuit designers to test and simulation such a

device based circuit performance.

In this paper, an analytical model of GAA silicon

NW-TFETs has been developed based on the

three-dimensional (3-D)

potential solution and the Kane’s

expression. For observing the validity of the model and the

different parameters impact on the device performance, we

have also compared the analytical model prediction with

the TCAD SenTaurus simulation results of the device to

verify the model validity.

2 STRUCTURE AND MODEL

2.1 Structure of GAA NW-TFET

The Figure1 shows the structure of GAA TFET with

silicon nanowire body. Figure1 (a) indicates 3-D structure of

the n-channel GAA NW-TFET. Figure1 (b) represents the

cross-section of the device with n-channel. In this paper,

n-TFET is considered so the doping profile along the axis

direction with the



doping in source,



doping in channel

and drain. Band-to-band tunneling (BTBT) happens in the

P/N junction at the source/channel region. Based on the

drift-diffusion (DD) theory, the electrons are moved toward

the drain thus the device can be divided into three regions: the

depletion region , the tunneling region  and the surplus

channel region .

Figure 1: (a) 3-D structure of the n-channel GAA Silicon

NW-TFET (b) Cross-section of the device and its division

into a depletion region , a tunneling region     

conventional GAA MOSFET region 

Energy bands with electron and hole quasi-Fermi energies

along the axis direction from the device simulator TCAD

SenTaurus are

demonstrated in Figure2. As shown, inversion

(

)

Drain

Gate

Source

(b)

Depletion

Tunneling

Source

P+

Gate Metal

Drain

N+





Sillicon Channel N+



Oxide

SiO

NSTI-Nanotech 2014, www.nsti.org, ISBN 978-1-4822-5827-1 Vol. 2, 2014

491

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