微处理器架构：从简单流水线到芯片多处理器

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"《微处理器架构 - 从简单流水线到芯片多处理器》由Jean-Loup Baer撰写，剑桥大学出版社于2009年12月7日出版，全面探讨了从简单的顺序短管道设计到先进的乱序超标量处理器的微处理器架构。书中涵盖了诸如注册重命名、预留站、重排序缓冲区、分支预测、指令调度、负载-存储推测、缓存层次结构中的延迟容忍设计以及单芯片多线程和多处理技术等关键主题。" 本书深入浅出地介绍了微处理器的核心概念，旨在让读者理解各种复杂的处理器设计策略。首先，书中详细讨论了乱序处理的政策和机制，如： 1. **注册重命名（Register Renaming）**：这是为了解决由于乱序执行导致的寄存器依赖问题，通过为每个物理寄存器分配多个虚拟寄存器来避免冲突。 2. **预留站（Reservation Stations）**：在乱序执行的处理器中，这些是用于存储中间操作结果和等待执行的操作的结构，以提高吞吐量。 3. **重排序缓冲区（Reorder Buffers）**：它们负责跟踪和恢复执行的指令顺序，确保最终结果按正确的程序顺序提交。接着，书中还涉及了提升性能的各种优化技术，包括： 4. **分支预测（Branch Predictors）**：预测分支指令的走向，减少因分支延迟而产生的空闲周期，从而提高处理器效率。 5. **指令调度（Instruction Scheduling）**：通过对指令进行重新排序和组合，优化执行效率，避免数据依赖和资源冲突。 6. **负载-存储推测（Load-Store Speculation）**：在确定数据可用性之前提前执行负载和存储操作，以减少整体延迟。此外，Baer教授还分析了如何应对单个和多个处理器的缓存层次结构中的延迟： 7. **缓存层次结构的设计选择与增强**：讨论了如何通过缓存层次结构的优化来减少内存访问延迟，如缓存替换策略、缓存预取等。书中还特别强调了单芯片多线程和多处理的最新发展： 8. **多线程（Multithreading）**：通过同时处理多个线程，提高了处理器资源利用率，减少了空闲时间。 9. **多处理器（Multiprocessing）**：特别是在单芯片多处理器（Chip Multiprocessors, CMPs）上的实现，讨论了如何在单一芯片上集成多个处理核心以提高整体性能和能效。 Jean-Loup Baer教授以概念思想为核心，配以评估性能影响的指标和实现示例，使读者能够从黑盒和算法层面理解这些工作原理。同时，他还提供了寄存器传输级的详细信息，帮助读者理解这些设计特征如何既增强了性能也增加了复杂性。这本书对于计算机科学领域的学生、研究人员和工程师来说，是一本宝贵的参考资料，它不仅提供理论知识，还包含了实践经验，有助于深入理解微处理器架构的内在机制。

xiv Preface

I thank Lauren Cowles and David Jou at Cambridge University Press for pro-

viding me with excellent anonymous reviews, and Shana Meyer and colleagues at

Aptara, Inc. – in particular, copy editor Joseph C. Fineman – for a smooth and timely

production process.

Jean-Loup Baer

Seattle, WA

August 2009

1 Introduction

Modern computer systems built from the most sophisticated microprocessors and

extensive memory hierarchies achieve their high performance through a combina-

tion of dramatic improvements in technology and advances in computer architec-

ture. Advances in technology have resulted in exponential growth rates in raw speed

(i.e., clock frequency) and in the amount of logic (number of transistors) that can be

put on a chip. Computer architects have exploited these factors in order to further

enhance performance using architectural techniques, which are the main subject of

this book.

Microprocessors are over 30 years old: the Intel 4004 was introduced in 1971.

The functionality of the 4004 compared to that of the mainframes of that period

(for example, the IBM System/370) was minuscule. Today, just over thirty years

later, workstations powered by engines such as (in alphabetical order and without

speciﬁc processor numbers) the AMD Athlon, IBM PowerPC, Intel Pentium, and

Sun UltraSPARC can rival or surpass in both performance and functionality the

few remaining mainframes and at a much lower cost. Servers and supercomputers

are more often than not made up of collections of microprocessor systems.

It would be wrong to assume, though, that the three tenets that computer archi-

tects have followed, namely pipelining, parallelism, and the principle of locality, were

discovered with the birth of microprocessors. They were all at the basis of the design

of previous (super)computers. The advances in technology made their implementa-

tions more practical and spurred further reﬁnements. The microarchitectural tech-

niques that are presented in this book rely on these three tenets to translate the

architectural speciﬁcation – the instruction set architecture – into a partition of static

blocks whose dynamic interaction leads to their intended behavior.

In the next few pages, we give an extremely brief overview of the advances in

technology that have led to the development of current microprocessors. Then, the

remainder of this chapter is devoted to deﬁning performance and means to mea-

sure it.

1.1 A Quick View of Technological Advances 3

Of course, in the more than sixty years of existence of stored program computers,

both the contents of the blocks and the basic instruction execution cycle sequence

have been optimized thoroughly. In this book, we shall look primarily at what can

be found on a microprocessor chip. At the outset, a microprocessor chip contained

the CPU. Over the years, the CPU has been enhanced so that it could be pipelined.

Several functional units have replaced the single ALU. Lower levels of the memory

hierarchy (caches) have been integrated on the chip. Recently, several microproces-

sors and their low-level caches coexist on a single chip, forming chip multiprocessors

(CMPs). Along with these (micro)architectural advances, the strict sequential exe-

cution cycle has been extended so that we can have several instructions proceed

concurrently in each of the basic steps. In Chapters 2 through 6, we examine the

evolution of single processor chips; Chapters 7 and 8 are devoted to multiprocessors.

1.1.2 Technological Advances

The two domains in which technological advances have had the most impact on the

performance of microprocessor systems have been the increases in clock frequency

and the shrinking of the transistor features leading to higher logic density. In a sim-

plistic way, we can state that increasing clock frequency leads to faster execution,

and more logic yields implementation of more functionality on the chip.

Figure 1.2 shows the evolution of the clock frequencies of the Intel micropro-

cessors from the inception of the 4004 in 1971 to the chip multiprocessors of 2003

and beyond. From 1971 to 2002, we see that processor raw speeds increased at an

exponential rate. The frequency of the 4004, a speck on the ﬁgure that cannot be

seen because of the scaling effect, was 1.08 MHz, a factor of 3,000 less than the 3.4

GHz of the Pentium 4. This corresponds roughly to a doubling of the frequency

every 2.5 years. To be fair, though, although the Pentium 4 was the fastest processor

in 2003, there were many mainframes in 1971 that were faster than the 4004. Some

supercomputers in the late 1960s, such as the IBM System 360/91 and Control Data

6600/7600 – two machines that will be mentioned again in this book – had frequen-

cies of over 100 MHz. However, if they were two orders of magnitude faster than

the 4004, they were about six orders of magnitude more expensive. After 2003, the

frequencies stabilize in the 3 GHz range. We shall see very shortly the reason for

such a plateau.

The number of transistors that can be put on a chip has risen at the same pace

as the frequency, but without any leveling off. In 1965, Gordon Moore, one of the

founders of Intel, predicted that “the number of transistors on a given piece of sili-

con would double every couple of years.” Although one can quibble over the “cou-

ple of years” by a few months or so, this prediction has remained essentially true and

is now known as Moore’s law. Figure 1.3 shows the exponential progression of tran-

sistors in the Intel microprocessors (notice the log scale). There is a growth factor

of over 2,000 between the 2,300 transistors of the Intel 4004 and the 1.7 billion tran-

sistors of the 2006 Intel dual-core Itanium (the largest number of transistors in the

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