TDA3x SR1.0：高级驾驶辅助系统（ADAS）SoC技术参考手册

需积分: 9 117 浏览量更新于2024-07-18 收藏 26.58MB PDF 举报

"TDA3x_SR1.0_NDA_TRM_vG.pdf 是一份关于TI公司的TDA3x SoC的高级驾驶辅助系统(ADAS)应用设备的技术参考手册，详细介绍了该芯片的设计、功能和子系统。" TDA3x是基于增强型OMAP架构的28纳米技术的ADAS应用设备，它与TDA2x家族共享一个共同的架构，为各种应用提供了从入门级到高性能的可扩展性。这个设备家族主要针对包括前视摄像头、智能后视摄像头、雷达和后视镜替换等ADAS应用。 TDA3x芯片由以下主要子系统组成： 1. **双数字信号处理器(DSP)C66x子系统**：提供强大的计算能力，处理复杂的算法和数据处理任务。 2. **嵌入式视觉引擎(EVE)加速器子系统**：专为视觉处理任务优化，如图像分析和目标识别。 3. **双Cortex-M4微处理器单元(MCU)子系统**：用于实时控制和低功耗操作，执行系统管理任务。 4. **视频输入捕获端口(VIP)**：用于接收和处理来自不同传感器的视频输入。 5. **显示子系统(DSS)**：支持多种显示器输出，可用于在车辆中显示ADAS信息。 6. **成像子系统(ISS)**：带有成像信号处理器(ISP)，负责图像校正、色彩管理和噪声抑制。 7. **调试子系统**：为开发和故障排除提供工具和支持。手册中还涵盖了以下主题： - **TDA3x的环境**：可能的工作条件和应用环境。 - **TDA3x描述**：对芯片的整体功能和设计特点的详细说明。 - **子系统的详细介绍**：每个子系统的功能、接口和工作原理。 - **内存管理**：包括内部和外部存储器接口，以及电源、复位和时钟管理。 - **系统和连接性外设**：如I/O端口、网络接口和其他通信通道。 - **TDA3x家族**：在TI ADAS产品线中的位置和与其他成员的关系。 - **设备标识**：如何识别不同的TDA3x设备型号。 - **封装特性概述**：封装尺寸、引脚配置和机械特性。这份技术参考手册对于理解TDA3x的功能、设计和使用至关重要，是开发者和工程师进行ADAS系统集成和应用开发的重要参考资料。通过深入研究手册，可以掌握如何利用TDA3x的强大性能来实现高效、安全的驾驶辅助解决方案。

TI Confidential — NDA Restrictions ECCN: 5E991

www.ti.com

6.1.6.1.2 Top-Level Requirements ........................................................................... 1657

6.1.6.1.3 Configuration ......................................................................................... 1658

6.1.6.1.4 Block Diagram ....................................................................................... 1659

6.1.6.2 Functional Description................................................................................... 1659

6.1.6.2.1 Configuration Interface.............................................................................. 1659

6.1.6.2.2 Counter Function .................................................................................... 1660

6.1.6.2.3 Timer Function ....................................................................................... 1661

6.1.6.2.4 System Trace Integration........................................................................... 1664

6.1.6.3 Use Case Examples ..................................................................................... 1666

6.1.6.3.1 Counter Enable ...................................................................................... 1666

6.1.6.3.2 Timer Enable......................................................................................... 1667

6.1.6.3.3 Periodic STM Export Enable....................................................................... 1668

6.1.6.3.4 Disabling the SCTM ................................................................................ 1668

6.1.6.4 SCTM Register Manual ................................................................................. 1669

6.1.6.4.1 SCTM Instance Summary .......................................................................... 1669

6.1.6.4.2 SCTM Registers ..................................................................................... 1669

6.1.7 Software Message and System Event Trace .............................................................. 1677

6.1.7.1 Introduction ............................................................................................... 1677

6.1.7.1.1 Overview.............................................................................................. 1677

6.1.7.1.2 Configuration ......................................................................................... 1677

6.1.7.1.3 Block Diagram ....................................................................................... 1677

6.1.7.2 Functional Description................................................................................... 1678

6.1.7.2.1 Connectivity .......................................................................................... 1678

6.1.7.2.2 SMSET Event Mapping............................................................................. 1678

6.1.7.2.3 Software Messages ................................................................................. 1679

6.1.7.2.4 SMSET Master Port................................................................................. 1680

6.1.7.2.5 SMSET Debug Features ........................................................................... 1680

6.1.7.2.6 Component Ownership ............................................................................. 1680

6.1.7.3 Use Case Examples ..................................................................................... 1681

6.1.7.3.1 Procedure to Enable System Event Capture .................................................... 1681

6.1.7.3.2 Procedure to Start and Stop System Event Capture from External Trigger Detection..... 1682

6.1.7.3.3 Procedure to Disable System Event Capture.................................................... 1682

6.1.7.4 SMSET Register Manual................................................................................ 1682

6.1.7.4.1 SMSET Instance Summary ........................................................................ 1682

6.1.7.4.2 SMSET Registers Mapping Summary ........................................................... 1682

6.1.7.4.3 SMSET Register Description ...................................................................... 1683

6.2 ARP32 CPU and Instruction Set ...................................................................................... 1687

6.2.1 Overview......................................................................................................... 1687

6.2.2 Features ......................................................................................................... 1688

6.2.3 Block Diagram .................................................................................................. 1688

6.2.4 Architecture ..................................................................................................... 1688

6.2.4.1 Interface Description..................................................................................... 1688

6.2.4.1.1 Data Memory Interface ............................................................................. 1690

6.2.4.1.2 Instruction Memory Interface....................................................................... 1690

6.2.4.2 Pipeline.................................................................................................... 1691

6.2.4.2.1 Overview.............................................................................................. 1691

6.2.4.2.2 Pipeline Operation................................................................................... 1691

6.2.4.2.3 Pipeline Interlocks ................................................................................... 1692

6.2.4.3 Data Format .............................................................................................. 1693

6.2.4.4 Endian Support........................................................................................... 1693

6.2.4.5 Architectural Register File .............................................................................. 1693

6.2.4.6 CPU Control Registers .................................................................................. 1693

6.2.4.6.1 Control Status Register (CSR)..................................................................... 1695

Contents SPRUHQ7G–April 2014–Revised December 2014

Submit Documentation Feedback

TI Confidential — NDA Restrictions ECCN: 5E991

www.ti.com

6.2.4.6.2 Interrupt Enable Register (IER).................................................................... 1696

6.2.4.6.3 Interrupt Flag Register (IFR) ....................................................................... 1697

6.2.4.6.4 Interrupt Set Register (ISR) ........................................................................ 1698

6.2.4.6.5 Interrupt Clear Register (ICR)...................................................................... 1699

6.2.4.6.6 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)................................. 1700

6.2.4.6.7 Interrupt Return Pointer Register (IRP)........................................................... 1700

6.2.4.6.8 Stack Pointer Register (SP)........................................................................ 1701

6.2.4.6.9 Global Data Pointer Register (GDP) .............................................................. 1701

6.2.4.6.10 Link Register (LR) ................................................................................... 1701

6.2.4.6.11 Loop 0 Start Address Register (LSA0) ........................................................... 1702

6.2.4.6.12 Loop 0 End Address Register (LEA0) ............................................................ 1702

6.2.4.6.13 Loop 0 Iteration Count Register (LCNT0) ........................................................ 1703

6.2.4.6.14 Loop 1 Start Address Register (LSA1) ........................................................... 1704

6.2.4.6.15 Loop 1 End Address Register (LEA1) ............................................................ 1704

6.2.4.6.16 Loop 1 Iteration Count Register (LCNT1) ........................................................ 1705

6.2.4.6.17 Loop 0 Iteration Count Reload Value Register (LCNT0RLD) ................................. 1705

6.2.4.6.18 Shadow Control Status Register (SCSR) ........................................................ 1706

6.2.4.6.19 NMI Shadow Control Status Register (NMISCSR) ............................................. 1707

6.2.4.6.20 CPU Identification Register (CPUID) ............................................................. 1708

6.2.4.6.21 Decode Program Counter Register (DPC)....................................................... 1709

6.2.4.6.22 Time Stamp Counter Registers (TSCL and TSCH)............................................. 1709

6.2.4.7 CPU Shadow Registers ................................................................................. 1711

6.2.4.8 Functional Units .......................................................................................... 1712

6.2.4.9 Instruction Fetch ......................................................................................... 1712

6.2.4.10 Alignment of 32-bit Instructions ........................................................................ 1713

6.2.4.11 Instruction Execution in Branch Delay Slot ........................................................... 1713

6.2.4.12 Address Space .......................................................................................... 1713

6.2.4.13 Program Counter Convention .......................................................................... 1714

6.2.4.14 Stack Pointer Convention............................................................................... 1714

6.2.4.15 Global Data Pointer Convention ....................................................................... 1715

6.2.4.16 Conditional Execution ................................................................................... 1715

6.2.4.17 Hardware Loop Acceleration ........................................................................... 1715

6.2.4.17.1 Overview.............................................................................................. 1715

6.2.4.17.2 Loop Registers....................................................................................... 1716

6.2.4.17.3 Loop Setup Instructions ............................................................................ 1716

6.2.4.17.4 Loop Operation ...................................................................................... 1716

6.2.4.17.5 Call and Branch within Loop Context............................................................. 1718

6.2.4.17.6 Dynamic Changes to Loop Iteration Count ...................................................... 1718

6.2.4.17.7 Interrupt Processing During HLA.................................................................. 1718

6.2.4.17.8 HLA Usage in Interrupt Context ................................................................... 1718

6.2.4.17.9 HLA Usage Restrictions ............................................................................ 1718

6.2.4.17.10 HLA Mapping Examples .......................................................................... 1719

6.2.4.18 Interrupts .................................................................................................. 1723

6.2.4.18.1 Overview.............................................................................................. 1723

6.2.4.18.2 Interrupt Processing................................................................................. 1724

6.2.4.18.3 Interrupt Acknowledgment ......................................................................... 1725

6.2.4.18.4 Interrupt Priorities ................................................................................... 1726

6.2.4.18.5 Interrupt Service Table (IST)....................................................................... 1727

6.2.4.18.6 Interrupt Flags ....................................................................................... 1727

6.2.4.18.7 Interrupt Behavior ................................................................................... 1728

6.2.4.18.8 Interrupt Context Save and Restore .............................................................. 1731

6.2.4.18.9 Nested Interrupts .................................................................................... 1733

6.2.4.18.10 Non-nested Interrupt Latency .................................................................... 1735

SPRUHQ7G–April 2014–Revised December 2014 Contents

Submit Documentation Feedback

TI Confidential — NDA Restrictions ECCN: 5E991

www.ti.com

6.2.5 Instruction Set .................................................................................................. 1735

6.2.5.1 Instruction Operation and Execution Notations ...................................................... 1735

6.2.5.2 Instruction Syntax and Opcode Notations ............................................................ 1737

6.2.5.3 Instruction Scheduling Restrictions .................................................................... 1737

6.2.5.3.1 Restrictions Applicable to a Branch Delay Slot.................................................. 1737

6.2.5.3.2 Restrictions on Loops Using Hardware Loop Assist (HLA) .................................... 1737

6.2.5.3.3 Restrictions on Other Types of Control Flow Instructions...................................... 1738

6.2.5.3.4 Restrictions for Write Data Bypass to Control Register Reads................................ 1738

6.2.5.3.5 Restrictions for Write Data Bypass to Shadow Register Reads............................... 1738

6.2.5.3.6 Restrictions for Link Register Update............................................................. 1738

6.2.5.4 Instruction Set Encoding ................................................................................ 1738

6.2.5.5 Instruction Descriptions ................................................................................. 1738

6.2.6 Clock, Reset, and Dynamic Power Management .......................................................... 1874

6.2.6.1 Introduction ............................................................................................... 1874

6.2.6.2 CPU Reset Modes ....................................................................................... 1874

6.2.6.3 Dynamic Power Management .......................................................................... 1876

6.2.7 Notes on Programming Model................................................................................ 1877

6.2.7.1 Booting .................................................................................................... 1877

6.2.7.2 Enabling and Disabling Interrupts...................................................................... 1877

6.2.7.2.1 Globally Enabling or Disabling Maskable Interrupts ............................................ 1877

6.2.7.2.2 Enabling or Disabling Individual Interrupts ....................................................... 1878

6.2.7.3 Stack Usage in Interrupt Service Routine ............................................................ 1878

6.2.7.4 General Restrictions ..................................................................................... 1879

6.3 VCOP CPU and Instruction Set ....................................................................................... 1879

6.3.1 Module Overview............................................................................................... 1879

6.3.2 Features ......................................................................................................... 1879

6.3.3 Block Diagram .................................................................................................. 1880

6.3.4 System Interfaces .............................................................................................. 1881

6.3.4.1 Interrupts ................................................................................................. 1881

6.3.4.2 Configuration Bus Slave Port .......................................................................... 1881

6.3.4.3 Performance Counter Interface ........................................................................ 1881

6.3.4.4 Data Memory Map ...................................................................................... 1882

6.3.5 Functional Description ......................................................................................... 1884

6.3.5.1 Scalar-Vector Architecture .............................................................................. 1884

6.3.5.1.1 Scalar Core .......................................................................................... 1884

6.3.5.1.2 Scalar-Vector Interaction ........................................................................... 1884

6.3.5.2 Vector Core Overview .................................................................................. 1885

6.3.5.2.1 Nested for Loop Model ............................................................................. 1885

6.3.5.2.2 Instruction Organization ............................................................................ 1887

6.3.5.3 Vector Control ............................................................................................ 1887

6.3.5.3.1 Repeat End Count................................................................................... 1887

6.3.5.3.2 Parameter Pointer ................................................................................... 1888

6.3.5.3.3 Switch Buffers........................................................................................ 1888

6.3.5.4 Vector-Scalar Synchronization ......................................................................... 1889

6.3.5.4.1 Wait for Vector Core Done ......................................................................... 1889

6.3.5.4.2 Wait for Vector Core Ready........................................................................ 1889

6.3.5.5 Vector Computation ..................................................................................... 1889

6.3.5.5.1 Vector Loop .......................................................................................... 1889

6.3.5.5.2 Vector Register Initialization ....................................................................... 1890

6.3.5.5.3 Address Generator (agen) ......................................................................... 1891

6.3.5.5.4 Vector Load .......................................................................................... 1892

6.3.5.5.5 Vector Arithmetic/Logic Operations .............................................................. 1898

6.3.5.5.6 Vector Store .......................................................................................... 1901

Contents SPRUHQ7G–April 2014–Revised December 2014

Submit Documentation Feedback

TI Confidential — NDA Restrictions ECCN: 5E991

www.ti.com

6.3.5.5.7 Table Lookup Operation ........................................................................... 1903

6.3.5.5.8 Histogram Operation ............................................................................... 1907

6.3.5.5.9 Circular Buffer Addressing Support ............................................................... 1910

6.3.5.5.10 Load/Store Address Alignment Constraints...................................................... 1911

6.3.5.6 Load/Store Buffer and Scheduling..................................................................... 1912

6.3.5.7 VCOP Per-Loop Overhead ............................................................................. 1914

6.3.5.8 VCOP Error Handling.................................................................................... 1915

6.3.5.9 Vector Operation Details ................................................................................ 1916

6.3.5.9.1 VABS.................................................................................................. 1916

6.3.5.9.2 VABSDIF ............................................................................................. 1916

6.3.5.9.3 VADD ................................................................................................. 1916

6.3.5.9.4 VADDH................................................................................................ 1916

6.3.5.9.5 VADDSUB ............................................................................................ 1917

6.3.5.9.6 VADD3 ................................................................................................ 1917

6.3.5.9.7 VADIF3................................................................................................ 1917

6.3.5.9.8 VAND ................................................................................................. 1917

6.3.5.9.9 VANDN................................................................................................ 1917

6.3.5.9.10 VAND3 ............................................................................................... 1918

6.3.5.9.11 VBINLOG ............................................................................................ 1918

6.3.5.9.12 VBITC................................................................................................. 1919

6.3.5.9.13 VBITDI ............................................................................................... 1919

6.3.5.9.14 VBITI ................................................................................................. 1919

6.3.5.9.15 VBITPK .............................................................................................. 1920

6.3.5.9.16 VBITR................................................................................................. 1920

6.3.5.9.17 VBITTR ............................................................................................... 1920

6.3.5.9.18 VBITUNPK .......................................................................................... 1921

6.3.5.9.19 VCMOV .............................................................................................. 1921

6.3.5.9.20 VCMPEQ ............................................................................................ 1921

6.3.5.9.21 VCMPGE ............................................................................................. 1921

6.3.5.9.22 VCMPGT ............................................................................................. 1922

6.3.5.9.23 VDINTRLV ........................................................................................... 1922

6.3.5.9.24 VDINTRLV2 .......................................................................................... 1923

6.3.5.9.25 VEXITNZ ............................................................................................. 1923

6.3.5.9.26 VINTRLV ............................................................................................. 1924

6.3.5.9.27 VINTRLV2 ........................................................................................... 1924

6.3.5.9.28 VINTRLV4............................................................................................ 1925

6.3.5.9.29 VLMBD ............................................................................................... 1925

6.3.5.9.30 VMADD .............................................................................................. 1926

6.3.5.9.31 VMAX ................................................................................................ 1926

6.3.5.9.32 VMAXSETF ......................................................................................... 1927

6.3.5.9.33 VMIN ................................................................................................. 1927

6.3.5.9.34 VMINSETF .......................................................................................... 1927

6.3.5.9.35 VMPY ................................................................................................. 1927

6.3.5.9.36 VMSUB .............................................................................................. 1928

6.3.5.9.37 VNOP ................................................................................................ 1928

6.3.5.9.38 VNOT ................................................................................................ 1928

6.3.5.9.39 VOR .................................................................................................. 1928

6.3.5.9.40 VOR3 ................................................................................................. 1929

6.3.5.9.41 VRND ................................................................................................ 1929

6.3.5.9.42 VSAD ................................................................................................. 1929

6.3.5.9.43 VSEL ................................................................................................. 1929

6.3.5.9.44 VSHF.................................................................................................. 1930

6.3.5.9.45 VSHFOR ............................................................................................. 1930

SPRUHQ7G–April 2014–Revised December 2014 Contents

Submit Documentation Feedback

TI Confidential — NDA Restrictions ECCN: 5E991

www.ti.com

6.3.5.9.46 VSHF16 .............................................................................................. 1930

6.3.5.9.47 VSIGN ................................................................................................ 1930

6.3.5.9.48 VSORT2 .............................................................................................. 1931

6.3.5.9.49 VSUB ................................................................................................. 1931

6.3.5.9.50 VSWAP .............................................................................................. 1931

6.3.5.9.51 VXOR ................................................................................................ 1931

6.3.6 Debug Support.................................................................................................. 1932

6.3.7 VCOP Register Manual........................................................................................ 1932

6.3.7.1 VCOP Instance Summary .............................................................................. 1932

6.3.7.2 VCOP Registers.......................................................................................... 1932

6.3.7.2.1 VCOP Registers Mapping Summary ............................................................. 1932

6.3.7.2.2 VCOP Register Description ....................................................................... 1933

7 Imaging Subsystem......................................................................................................... 1940

8 Video Input Port.............................................................................................................. 1941

8.1 VIP Overview ............................................................................................................ 1942

8.2 VIP Environment ........................................................................................................ 1943

8.3 VIP Integration........................................................................................................... 1945

8.4 VIP Functional Description ............................................................................................ 1946

8.4.1 VIP Block Diagram ............................................................................................. 1946

8.4.2 VIP Software Reset ............................................................................................ 1947

8.4.3 VIP Power and Clocks Management ....................................................................... 1947

8.4.3.1 VIP Clocks ................................................................................................ 1947

8.4.3.2 VIP Idle Mode ............................................................................................ 1948

8.4.3.3 VIP StandBy Mode....................................................................................... 1948

8.4.4 VIP Slice......................................................................................................... 1948

8.4.4.1 VIP Slice Processing Path Overview.................................................................. 1948

8.4.4.2 VIP Slice Processing Path Multiplexers............................................................... 1950

8.4.4.2.1 VIP_CSC Multiplexers ............................................................................. 1950

8.4.4.2.2 VIP_SC Multiplexer.................................................................................. 1950

8.4.4.2.3 Output to VPDMA Multiplexers .................................................................... 1950

8.4.4.3 VIP Slice Data Path Example .......................................................................... 1950

8.4.4.3.1 TEST1................................................................................................. 1950

8.4.4.3.2 TEST2................................................................................................. 1951

8.4.4.3.3 TEST3................................................................................................. 1952

8.4.4.3.4 TEST4................................................................................................. 1953

8.4.4.3.5 TEST5................................................................................................. 1954

8.4.4.3.6 TEST6................................................................................................. 1955

8.4.4.3.7 TEST7................................................................................................. 1956

8.4.4.3.8 TEST8................................................................................................. 1957

8.4.4.3.9 TEST9................................................................................................. 1958

8.4.5 VIP Parser....................................................................................................... 1959

8.4.5.1 VIP_PARSER Features ................................................................................. 1959

8.4.5.2 VIP_PARSER Functional Description ................................................................. 1960

8.4.5.2.1 Repacker ............................................................................................. 1960

8.4.5.2.2 Analog Video......................................................................................... 1962

8.4.5.2.3 Digitized Video ....................................................................................... 1962

8.4.5.2.4 Frame Buffers........................................................................................ 1964

8.4.5.2.5 Input Data Interface ................................................................................. 1965

8.4.5.2.6 BT.656 Style Embedded Sync..................................................................... 1976

8.4.5.2.7 Source Multiplexing ................................................................................. 1980

8.4.5.2.8 Channel ID Extraction for 2x/4x Multiplexed Source............................................ 1985

8.4.5.2.9 Embedded Sync Mux Modes and Data Bus Widths ............................................ 1986

8.4.5.2.10 Ancillary and Active Video Cropping.............................................................. 1986

Contents SPRUHQ7G–April 2014–Revised December 2014

Submit Documentation Feedback

剩余5365页未读，继续阅读

月光下的麦克

粉丝: 883
资源: 25

TDA3x SR1.0：高级驾驶辅助系统（ADAS）SoC技术参考手册

TDA3x Silicon Revision

SmartConfigCC3X

3X官方原版Recovery.rar

tda3x device trm

tda2030a_sch_lib

tda4vm c7x应用

最新资源