变压器基础：振荡器与分频器设计新策略

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《基于变压器的振荡器与分频器设计技术》由Howard Cam Luong和Jun Yin共同撰写，两位作者分别来自香港科技大学电子工程系以及澳门大学的混合信号模拟集成电路国家重点实验室。该著作聚焦于利用变压器原理进行振荡器和频率分频器的设计，这是一种在射频（RF）和CMOS技术领域中的关键设计策略。在书中，作者详细探讨了如何利用变压器的特性来提高电路的性能，包括其在信号频率变换、隔离度增强、以及在小型化和低功耗应用中的优势。变压器作为无源元件，能够实现电感和电容的替代，从而实现频率的精确控制和信号传输的可靠性。对于振荡器，这可能涉及到多谐振荡、LC振荡器的改进，通过变压器实现相位锁定或频率自稳定功能。分频器设计方面，变压器可以提供灵活的分频比，并且能减少对外部组件的需求，如电阻和电容器，这对于在高频率和复杂系统中保持信号完整性至关重要。书中还可能涉及环形变压器、推挽式变压器等不同结构的应用，以及如何优化这些变压器在实际电路中的性能。本书涵盖了理论分析、设计方法、实验验证和案例研究，旨在为读者提供一个全面的框架，帮助他们理解和掌握基于变压器的振荡器和分频器设计技巧。它不仅适合于从事射频前端设计的专业工程师，也对希望深入了解CMOS与RF技术交叉领域的研究人员具有参考价值。此外，本书提供了丰富的图表、公式和实用设计指导，便于读者在实践中应用所学知识。版权信息表明，该书受到了Springer国际出版公司的出版支持，所有内容受到版权保护，未经许可不得复制或以任何形式进行传播。整体而言，《基于变压器的振荡器和分频器设计技术》是一本深度剖析该领域核心概念和技术的权威之作。

problem with insufﬁcient frequency locking range due to their desirable high tank Q

for low power consumption and narrowband ﬁltering. At input frequency of around

60 GHz, the typical locking range of LC-ILFDs repor ted is around 12 % [17, 18].

In this book, in-depth description and discussion of transformer-based design

techniques that enable CMOS VCOs and ILFDs to achieve state-of-the-art perfor-

mance in terms of low supply voltage, low-power consumption, good phase noise,

high operation frequencies, and wide frequency tuning range and locking range are

presented. To illustrate the usefulness of these transformer-based design tech-

niques, design consideration and optimization of various VCOs and dividers for

different applications together with their measured perform ance are discussed in

detail, focusing on not only ultra-low supply voltage but also ultrawide frequency

tuning range and locking range at high frequencies.

1.2 Book Organization

This book is organized as follows. Chapter 2 will introduce how to design, simulate,

and characterize on-chip inductors and transformers in CMOS process, including

step-by-step procedures to simulate and model the passive devices for circuit design

and to verify the model based on silicon measurement. In Chap. 3, the phase-noise

analysis and design consideration of VCOs and quadrature VCOs (QVCOs) will be

reviewed, and the performance degradation with the scaling down of V

will be

discussed in detail. Chapter 4 introduces the principle of ILFDs and Miller dividers

and analyzes their locking range based on the phasor diagram. To demonstrate the

usefulness of the transformer-based design techniques, detailed design consider-

ations and measured results of a couple selected low-voltage high-performance

VCOs and QVCOs using transformer feedback will be presented in Chap. 5.

Chapters 6 and 7 will focus on the designs of transformer-based dual-mode or

multimode VCOs for wideband applications. In Chap. 8, desi gn examples for

ILFDs using transformer technique to achieve either low-voltage or wide locking

range will be discussed. Finally, conclusion will be drawn in Chap. 9, from which

recommendations for future work will be mad e.

References

1. Packan, P. (2007, December). Device and circuit interactions. IEEE International Electron

Device Meeting Short Course: Performance Boosters for Advanced CMOS Devices.

2. Carlson, E. J., Strunz, K., & Otis, B. P. (2010). A 20 mV input boost converter with efﬁcient

digital control for thermoelectric energy harvesting. IEEE Journal of Solid-State Circuits, 45,

741–750.

3. Zhang, F., Wang, K., Koo, J., Miyahara, Y., & Otis, B. (2013). A 1.6mW 300mV-supply

2.4GHz receiver with 94dBm sensitivity for energy-harvesting applications. IEEE ISSCC

Digest of Technical Papers, pp. 456–457.

4 1 Introduction

4. Wireless LAN medium access control (MAC) and physical layer (PHY) speciﬁcations, amend-

ment 3: Enhancements for very high throughput in the 60 GHz band, IEEE Std 802.11ad

(2012). New York: IEEE.

5. Wireless medium access control (MAC) and physical layer (PHY) speciﬁcations for high rate

wireless area network, amendment 2, IEEE 802.15.3c

. (2009). New York: IEEE.

6. Staszewski, R. B., Hung, C.-M., Maggio, K., Wallberg, J., Leipold, D., & Balsara, P. T. (2004).

All-digital phase-domain TX frequency synthesizer for bluetooth radios in 0.13μm CMOS.

IEEE ISSCC Digest of Technical Papers, pp. 272–273.

7. Wu, W., Bai, X., Staszewski, R. B., & Long, J. R. (2013). A 56.4-to-63.4GHz spurious-free

all-digital fractional-N PLL in 65nm CMOS. IEEE ISSCC Digest of Technical Papers,

pp. 352–353.

8. Rategh, H. R., Samavati, H., & Lee, T. H. (2000). A CMOS frequency synthesizer with an

injection-locked frequency divider for a 5-GHz wireless LAN receiver. IEEE Journal of Solid-

State Circuits, 35, 780–787.

9. Tiebout, M. (2004). A CMOS direct injection-locked oscillator topology as high-frequency

low-power frequency divider. IEEE Journal of Solid-State Circuits, 39, 1170–1174.

10. Kim, D., Kim, J., & Cho, C. (2008). A 94 GHz locking hysteresis-assisted and tunable CML

static divider in 65 nm SOI CMOS. IEEE ISSCC Digest of Technical Papers, pp. 460–461.

11. Ghilioni, A., Mazzanti, A., & Svelto, F. (2013). Analysis and design of mm-wave frequency

dividers based on dynamic latches with load modulation. IEEE Journal of Solid-State Circuits,

48, 1842–1850.

12. Borremans, J., Vengattaramane, K., Giannini, V., Debaillie, B., Thillo, W. V., & Craninckx,

J. (2010). A 86 MHz–12 GHz digital-intensive PLL for software-deﬁned radios, using a

6 fJ/step TDC in 40 nm digital CMOS. IEEE Journal of Solid-State Circuits, 45, 2116–2129.

13. Yu, S.-A., Baeyens, Y., Weiner, J., Koc, U.-V., Rambaud, M., Liao, F.-R., et al. (2011). A

single-chip 125-MHz to 32-GHz signal source in 0.18-μ m SiGe BiCMOS. IEEE Journal of

Solid-State Circuits, 46, 598–614.

14. Cao, C., & O, K. K. (2006). Millimeter-wave voltage-controlled oscillators in 0.13-μm CMOS

technology. IEEE Journal of Solid-State Circuits, 41(6), 1297–1304.

15. Kim, D. D., Kim, J., Plouchart, J.-O., Cho, C., Li, W., Lim, D., et al. (2007). A 70GHz

manufacturable complementary LC-VCO with 6.14GHz tuning range in 65nm SOI CMOS .

IEEE ISSCC Digest of Technical Papers, pp. 540–541.

16. Li, L., Reynaert, P., & Steyaert, M. S. J. (2009). Design and analysis of a 90 nm mm-wave

oscillator using inductive-division LC tank. IEEE Journal of Solid-State Circuits, 44,

1950–1958.

17. Gu, Q., Xu, Z., Huang, D., LaRocca, T., Wang, N.-Y., Hant, W., et al. (2008). A low power

V-band CMOS frequency divider with wide locking range and accurate quadrature output

phases. IEEE Journal of Solid-State Circuits, 43, 991–998.

18. Rong, S., Ng, A. W. L., & Luong, H. C. (2009). 0.9 mW 7 GHz and 1.6 mW 60 GHz frequency

dividers with locking-range enhancement in 0.13 μm CMOS. IEEE ISSCC Digest of Technical

Papers, pp. 96–97.

References 5

Chapter 2

Transformer Design and Characterization

in CMOS Process

2.1 Background

On-chip inductors have become essential in RF system-on-chip design and inte-

gration. As compared with off-chip inductors on the printed circuit board (PCB) or

bondwire inductors, the use of on-chip inductors prevents degradation of circuit

performance due to the loss and the parasitics from the chip interface. Moreover,

high-level integration with on-chip inductors can not only signiﬁcantly reduce the

cost and the form factor but also improve the reliability of the whole wireless

systems.

Unfortunately, on-chip inductors suffer from a low quality factor Q, which

would result in performance degradation in terms of noise, gain, and power

consumption. As a consequence, modern RF CMOS processes provide one or two

thick top metal layers far above the lossy substrate to improve the quality factor Q

and the self-resonant frequency of the on-chip inductors [1, 2]. In addition, due to

its relatively narrowband characteristics, on-chip inductors may not be suitable for

wideband applications, such as multiband, multimode, or software-deﬁned radios.

As potential replacement and improvement of on-chip inductors, integrated

transformers have recently been considered and widely used in wideband RF and

mm-Wave circuits and systems. Their main applications include (1) impedance

transformation in the impedance matching network, (2) ampliﬁcation for voltage or

current signal, (3) balun for on-ch ip single-ended to differential or differential to

single-ended signal transformation, and (4) high-order resonant tank to obtain either

multiple narrowband or wideband frequency response of amplitude and phase for

many circuits, including LNAs, VCOs, frequency dividers, frequency

multipliers, etc.

Figure 2.1a shows the schematic symbol of an ideal N:1 transformer, where

N ¼V

is deﬁned as the turn ratio between the primary coil and the secondary

coil. Since an ideal transformer is passive and no energy losses occur during the

voltage and current transformation, the current ratio I

equals to N. As a result,

H.C. Luong, J. Yin, Transformer-Based Design Techniques for Oscillators

and Frequency Dividers, DOI 10.1007/978-3-319-15874-7_2

magnetic ﬂux in integrated transformers, the coupling coefﬁcient is always sub-

stantially smaller than one [3].

Figure 2.3 shows another equivalent circuit model of the transformer

that employs an ideal transformer. Here, the ideal transformer with a turn r atio

N ¼ M=L

¼ k

ﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ

an d the inductance k

represents the coupling effect

between prima ry and secondary coils, while the inductance (1k

models the

leakage ﬂux that does not contribute the magnetic coupling. It is easily proved that

the equivalent model as shown in Fig. 2.3 is mathematically the same as the

T-model. As shown in the following chapters, the proper choice of the equival ent

models can facilitate the circuit calculation.

It is worthwhile to note the meaning of the dots in the transformer symbols in

Fig. 2.1. Assuming k is always positive, the dots should be denoted in such a way

that when the currents are sent into the dotted terminals from both the primary and

secondary coils, the generated magnetic ﬂuxes from both coils should go in the

same direction which reinforce each other [4]. Figure 2.4 shows the example to

determine the dot location based on this convention.

2.2 Transformer Layo ut

The common ways to realize integrated transformers are illustrated in Figs. 2.5, 2.6,

and 2.7, which offer different tradeoffs on self-inductances, magnetic coupling

coefﬁcient, inter-coil and coil-to-substrate capacitances, sel f-resonant frequencies,

and chip area [5]. Here, all the layouts are based on the differential conﬁgurations

since they are commonly used in VCOs and frequency dividers with balanced

differential outputs.

Figure 2.5 shows an interleaved transformer layout. Both the primary and

secondary coils are implemented with the same metal layer. As for on-chip inductor

design considerations [2], the thick top metal layer is typically used for maximum

quality factor Q and high self-resonant frequency because it has much smaller

square resistance than other metal layers and far away from the low resistance

substrate in CMOS process. When the metal traces need to be crossed over, the

lower metal layer can be used as a bridge. Since the interleaved conﬁguration

allows large common periphery between the primary and secondary coils, it can

P+

P−

S+

S−

-M

Fig. 2.2 T-model of the

transformer

2.2 Transformer Layout 9

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