TMS320F281X 数字信号处理器数据手册

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"TMS320F281X系列是TI（Texas Instruments）公司推出的数字信号处理器（Digital Signal Processors），主要包括TMS320F2810、TMS320F2811和TMS320F2812等型号。这些处理器属于TMS320C281X家族，适用于各种数字信号处理应用。该数据手册（Data Manual）提供了详细的设备信息，涵盖了硬件设计、功能特性和操作指南等内容。文档修订历史显示，此版本为SPRS174O，较之前的SPRS174N版本有若干技术更新和修改，包括ADC RES EXT描述的更新、安全性的额外注解、32位CPU定时器描述的调整以及电源管理等方面的变化。" TMS320F281X系列是高性能的浮点数字信号处理器，主要特点包括： 1. **高性能浮点运算能力**：TMS320F281X拥有强大的浮点计算单元，适合于需要实时处理复杂算法的领域，如电机控制、图像处理、通信系统等。 2. **丰富的外设接口**：这些处理器集成了多种外设接口，如模拟到数字转换器（ADC）、串行通信接口（SPI）、通用输入输出（GPIO）等，便于与外部传感器和控制器通信。 3. **高效能CPU**：32位CPU提供高频率的运算速度，支持多个CPU定时器，可实现精确的时间控制。 4. **内存结构**：内建SRAM，用于存储程序运行时的数据和指令，同时可能有外部扩展存储器接口，如ADCRESEXT在表2-2中的描述进行了修改。 5. **安全特性增强**：在第3.2.11节关于安全性的内容中增加了新的注解，可能涉及到处理器的安全保护机制或数据加密功能。 6. **电源管理优化**：更新了最大电流消耗的计算公式，特别是在IDLE状态下，对IDD Max值进行了调整，有利于低功耗设计。 7. **调试支持**：新增了6.8节，详细说明了在没有信号缓冲的情况下如何连接仿真器进行调试，这为开发过程中的问题排查提供了便利。 8. **其他修改**：还包括对32位CPU定时器描述的修改，如图3-6和4-8的更新，以及4.6节最大比特率公式的修正，确保了处理器在不同工作模式下的准确性和效率。 TMS320F281X系列处理器结合了高性能处理能力和灵活的外设配置，是面向实时信号处理应用的理想选择。其不断更新的技术文档反映了TI对于产品持续改进的承诺，以满足不断变化的市场需求和技术挑战。

Introduction

April 2001 − Revised July 2007SPRS174O

2.3.3 Pin Assignments for the PBK Package

The TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-pin PBK low-profile quad

flatpack (LQFP) pin assignments are shown in Figure 2−3. See Table 2−2 for a description of each pin’s

function(s).

96 65

128

DDAIO

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFM

ADCREFP

AVSSREFBG

AVDDREFBG

DDA1

SSA1

ADCRESEXT

MDRA

MDXA

MCLKRA

MFSXA

MCLKXA

MFSRA

DDIO

SPICLKA

SPISTEA

SPISIMOA

SPISOMIA

TDO

TMS

XCLKOUT

TCLKINA

TDIRA

CAP1_QEP1

T2PWM_T2CMP

T1PWM_T1CMP

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

SCIRXDB

SCITXDB

CANRXA

CAP2_QEP2

CAP3_QEPI1

T1CTRIP_PDPINTA

DDIO

T2CTRIP/ EVASOC

C1TRIP

C2TRIP

C3TRIP

TDI

PWM7

PWM8

PWM9

PWM10

PWM11

PWM12

T3PWM_T3CMP

T4PWM_T4CMP

CAP4_QEP3

CAP5_QEP4

CAP6_QEPI2

C4TRIP

C5TRIP

C6TRIP

DDIO

TEST2

TEST1

DD3VFL

TDIRB

TCLKINB

X1/XCLKIN

T3CTRIP_PDPINTB

CANTXA

T4CTRIP

/EVBSOC

127

126

125

124

123

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

122

TESTSEL

TRST

TCK

EMU0

XF_XPLLDIS

DDIO

EMU1

XINT1_XBIO

XNMI_XINT13

XINT2_ADCSOC

SCITXDA

SCIRXDA

XRS

DD1

SS1

ADCBGREFIN

SSA2

DDA2

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCLO

SSAIO

Figure 2−3. TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP

(Top View)

Introduction

April 2001 − Revised July 2007SPRS174O

Table 2−2. Signal Descriptions

†

(Continued)

NAME DESCRIPTIONPU/PD

I/O/Z

‡

PIN NO.

NAME DESCRIPTIONPU/PD

I/O/Z

‡

128-PINP

176-PINP

179-PING

XINTF SIGNALS (2812 ONLY) (CONTINUED)

XMP/MC F1 17 − I PD

Microprocessor/Microcomputer Mode Select.

Switches between microprocessor and

microcomputer mode. When high, Zone 7 is enabled

on the external interface. When low, Zone 7 is

disabled from the external interface, and on-chip

boot ROM may be accessed instead. This signal is

latched into the XINTCNF2 register on a reset and

the user can modify this bit in software. The state of

the XMP/MC

pin is ignored after reset.

XHOLD E7 159 − I PU

External Hold Request. XHOLD, when active (low),

requests the XINTF to release the external bus and

place all buses and strobes into a high-impedance

state. The XINTF will release the bus when any

current access is complete and there are no pending

accesses on the XINTF.

XHOLDA K10 82 − O/Z −

External Hold Acknowledge. XHOLDA is driven

active (low) when the XINTF has granted a XHOLD

request. All XINTF buses and strobe signals will be

in a high-impedance state. XHOLDA

is released

when the XHOLD

signal is released. External

devices should only drive the external bus when

XHOLDA

is active (low).

XZCS0AND1 P1 44 − O/Z −

XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1

is active (low) when an access to the XINTF Zone 0

or Zone 1 is performed.

XZCS2 P13 88 − O/Z −

XINTF Zone 2 Chip Select. XZCS2 is active (low)

when an access to the XINTF Zone 2 is performed.

XZCS6AND7 B13 133 − O/Z −

XINTF Zone 6 and Zone 7 Chip Select.

XZCS6AND7

is active (low) when an access to the

XINTF Zone 6 or Zone 7 is performed.

XWE N11 84 − O/Z −

Write Enable. Active-low write strobe. The write

strobe waveform is specified, per zone basis, by the

Lead, Active, and Trail periods in the XTIMINGx

registers.

XRD M3 42 − O/Z −

Read Enable. Active-low read strobe. The read

strobe waveform is specified, per zone basis, by the

Lead, Active, and Trail periods in the XTIMINGx

registers. NOTE: The XRD

and XWE signals are

mutually exclusive.

XR/W N4 51 − O/Z −

Read Not Write Strobe. Normally held high. When

low, XR/W

indicates write cycle is active; when high,

XR/W

indicates read cycle is active.

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled

in boundary scan mode.

Introduction

April 2001 − Revised July 2007 SPRS174O

Table 2−2. Signal Descriptions

†

(Continued)

NAME DESCRIPTIONPU/PD

I/O/Z

‡

PIN NO.

NAME DESCRIPTIONPU/PD

I/O/Z

‡

128-PINP

176-PINP

179-PING

XINTF SIGNALS (2812 ONLY) (CONTINUED)

XREADY B6 161 − I PU

Ready Signal. Indicates peripheral is ready to

complete the access when asserted to 1. XREADY

can be configured to be a synchronous or an

asynchronous input. See the timing diagrams for

more details.

JTAG AND MISCELLANEOUS SIGNALS

X1/XCLKIN K9 77 58 I

Oscillator Input − input to the internal oscillator. This

pin is also used to feed an external clock. The 28x

can be operated with an external clock source,

provided that the proper voltage levels be driven on

the X1/XCLKIN pin. It should be noted that the

X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V)

core digital power supply (V

), rather than the

3.3-V I/O supply (V

DDIO

). A clamping diode may be

used to clamp a buffered clock signal to ensure that

the logic-high level does not exceed V

(1.8 V or

1.9 V) or a 1.8-V oscillator may be used.

X2 M9 76 57 O Oscillator Output

XCLKOUT F11 119 87 O −

Output clock derived from SYSCLKOUT to be used

for external wait-state generation and as a

general-purpose clock source. XCLKOUT is either

the same frequency, 1/2 the frequency, or 1/4 the

frequency of SYSCLKOUT. At reset, XCLKOUT =

SYSCLKOUT/4. The XCLKOUT signal can be

turned off by setting bit 3 (CLKOFF) of the

XINTCNF2 register to 1. Unlike other GPIO pins, the

XCLKOUT pin is not placed in a high impedance

state during reset.

TESTSEL A13 134 97 I PD

Test Pin. Reserved for TI. Must be connected to

ground.

XRS D6 160 113 I/O PU

Device Reset (in) and Watchdog Reset (out).

Device reset. XRS

causes the device to terminate

execution. The PC will point to the address

contained at the location 0x3FFFC0. When XRS

brought to a high level, execution begins at the

location pointed to by the PC. This pin is driven low

by the DSP when a watchdog reset occurs. During

watchdog reset, the XRS

pin will be driven low for the

watchdog reset duration of 512 XCLKIN cycles.

The output buffer of this pin is an open-drain with an

internal pullup (100 µA, typical). It is recommended

that this pin be driven by an open-drain device.

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled

in boundary scan mode.

Introduction

April 2001 − Revised July 2007SPRS174O

Table 2−2. Signal Descriptions

†

(Continued)

NAME DESCRIPTIONPU/PD

I/O/Z

‡

PIN NO.

NAME DESCRIPTIONPU/PD

I/O/Z

‡

128-PINP

176-PINP

179-PING

JTAG AND MISCELLANEOUS SIGNALS (CONTINUED)

TEST1 M7 67 51 I/O −

Test Pin. Reserved for TI. On F281x devices, TEST1

must be left unconnected. On C281x devices, this

pin is a “no connect (NC)” (i.e., this pin is not

connected to any circuitry internal to the device).

TEST2 N7 66 50 I/O −

Test Pin. Reserved for TI. On F281x devices, TEST2

must be left unconnected. On C281x devices, this

pin is a “no connect (NC)” (i.e., this pin is not

connected to any circuitry internal to the device).

JTAG

TRST B12 135 98 I PD

JTAG test reset with internal pulldown. TRST, when

driven high, gives the scan system control of the

operations of the device. If this signal is not

connected or driven low, the device operates in its

functional mode, and the test reset signals are

ignored.

NOTE: Do not use pullup resistors on TRST

; it has

an internal pulldown device. TRST

is an active high

test pin and must be maintained low at all times

during normal device operation. In a low-noise

environment, TRST

may be left floating. In other

instances, an external pulldown resistor is highly

recommended. The value of this resistor should be

based on drive strength of the debugger pods

applicable to the design. A 2.2-kΩ resistor generally

offers adequate protection. Since this is

application-specific, it is recommended that each

target board be validated for proper operation of the

debugger and the application.

TCK A12 136 99 I PU JTAG test clock with internal pullup

TMS D13 126 92 I PU

JTAG test-mode select (TMS) with internal pullup.

This serial control input is clocked into the TAP

controller on the rising edge of TCK.

TDI C13 131 96 I PU

JTAG test data input (TDI) with internal pullup. TDI

is clocked into the selected register (instruction or

data) on a rising edge of TCK.

TDO D12 127 93 O/Z −

JTAG scan out, test data output (TDO). The contents

of the selected register (instruction or data) is shifted

out of TDO on the falling edge of TCK.

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled

in boundary scan mode.

剩余172页未读，继续阅读

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