ATmega-8位单片机全功能指南：数据操作与寄存器详解

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本文档全面介绍了Atmel公司生产的Atmega 8位单片机，一种高性能、低功耗的微控制器系列，基于先进的RISC架构设计。Atmega-8271J-AVR-ATmega型号单片机具有显著的特性，包括： 1. **强大的指令集**：它拥有131条高效能指令，能够在单个时钟周期内执行，显著提高了处理速度，支持高达20MIPS的处理性能，即使在20MHz的工作频率下也能保持高速运行。 2. **通用寄存器**：单片机内置32个8位工作寄存器，这些寄存器为数据操作提供了充足的存储空间，支持全静态操作模式，便于编程和数据管理。 3. **非易失性内存**：它配备了多种类型的非易失性存储区域，包括4/8/16/32KB的可系统编程Flash，用于长期保存程序代码；256/512/512/1KB的EEPROM，提供数据持久存储；以及512/1K/1K/2KBytes的内部SRAM，方便程序临时数据的存放。 4. **存储器耐久性**：Flash和EEPROM具有较高的写入/擦除循环次数，数据在85°C下可保持20年，而在25°C环境下可达100年，确保了长时间的数据可靠性。 5. **可编程启动区**：带有独立锁位的可选引导代码区域，提供了软件安全保护的功能。 6. **系统编程**：通过片上引导程序，实现了方便的在系统编程（ISP），允许用户在运行时更新程序。 7. **读写操作**：支持真正在写操作期间读取数据，即所谓的“真读-写”操作，提高了编程效率。 8. **软件安全**：编程锁定机制确保了软件的安全性。 9. **QTouch支持**：集成Atmel QTouch库，支持电容式触摸按钮、滑块和轮盘控制，最多可提供64个传感器通道，适用于触控输入设备的设计。 10. **外设功能**：具备两个独立预分频计数器和一个16位计数器，分别支持8位和16位定时器/计数器功能，满足不同应用场景的需求。通过这个文档，开发者可以深入了解Atmega 8位单片机的基础构造、工作原理以及其丰富的功能特性，有助于优化设计、提高开发效率和产品质量。无论是对于初学者还是经验丰富的工程师，这份文档都是深入理解和使用Atmega系列单片机的重要参考资料。

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271J-AVR- ATmega-Datasheet_11/2015

7.7.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four

clock cycles the program vector address for the actual interrupt handling routine is executed. During this four

clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt

routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in

sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in

addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program

Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in

SREG is set.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271J-AVR- ATmega-Datasheet_11/2015

8.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM

access is performed in two clk

CPU

cycles as described in Figure 8-4.

Figure 8-4. On-chip Data SRAM Access Cycles

8.4 EEPROM Data Memory

The ATmega48A/PA/88A/PA/168A/PA/328/P contains 256/512/512/1Kbytes of data EEPROM memory. It is

organized as a separate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described

in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM

Control Register.

”Memory Programming” on page 280 contains a detailed description on EEPROM Programming in SPI or

Parallel Programming mode.

8.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 8-2. A self-timing function, however, lets the user

software detect when the next byte can be written. If the user code contains instructions that write the EEPROM,

some precautions must be taken. In heavily filtered power supplies, V

is likely to rise or fall slowly on power-

up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for

the clock frequency used. See ”Preventing EEPROM Corruption” on page 21 for details on how to avoid

problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the

description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.

When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

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