Spartan-6 FPGA配置指南

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"Spartan-6 FPGA Configuration User Guide.pdf 是一份由Xilinx公司发布的用户指南，主要针对Spartan-6 FPGA的配置过程进行详细阐述。这份文档的版本为v2.2，发布日期为2010年7月30日。文档的目的是帮助用户在开发与Xilinx硬件设备协同工作的设计时使用Spartan-6 FPGA。" 本文档的核心内容涵盖了Spartan-6 FPGA的配置流程和技术细节，包括但不限于以下几个关键知识点： 1. **Spartan-6 FPGA概述**：Spartan-6系列是Xilinx公司的一款中低端FPGA（Field-Programmable Gate Array）产品，它提供了一系列的功能和性能选项，适用于各种嵌入式系统、通信、视频处理和工业应用。 2. **配置方法**：Spartan-6 FPGA可以通过多种方式配置，如JTAG（Joint Test Action Group）、SPI（Serial Peripheral Interface）、Parallel、BPI（Boot PROM Interface）等。每种方法都有其特定的适用场景和优势，用户需要根据项目需求选择合适的配置方式。 3. **配置流程**：配置过程通常包括初始化、加载配置数据和激活配置等步骤。这些步骤可能涉及到硬件接口设置、配置文件的生成以及与硬件的交互。 4. **配置工具**：Xilinx提供了如Vivado、ISE（Integrated Software Environment）等软件工具，用于生成配置文件和管理配置过程。这些工具通常具有图形用户界面，使得设计者可以方便地进行FPGA的设计和配置。 5. **错误处理与调试**：文档中会包含如何识别和解决配置过程中可能出现的问题，例如配置失败、时序错误等，并可能提供一些调试技巧。 6. **知识产权保护**：Xilinx强调文档的使用权限，禁止未经许可的复制、分发或以任何形式传播。此外，他们不对文档中的错误或遗漏承担责任，且保留随时更新文档而不事先通知的权利。 7. **技术支持与更新**：虽然Xilinx不保证对文档中的错误进行修正或提供更新通知，但通常他们会提供技术支持和帮助以解决用户在使用过程中遇到的问题。 "Spartan-6 FPGA Configuration User Guide.pdf" 是一个详细的技术参考资料，对于理解和使用Spartan-6 FPGA的配置过程至关重要，无论是初学者还是经验丰富的工程师都能从中获取有价值的信息。

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Chapter 1: Configuration Overview

The Slave SelectMAP mode is a simple x8- or x16-bit-wide processor peripheral interface,

including a chip-select input and a read/write control input. The Slave Serial mode is

extremely simple, consisting only of a clock and serial data input.

JTAG Connection

The four-wire JTAG interface is common on board testers and debugging hardware. In fact,

the Xilinx programming cables for Spartan-6 FPGAs, listed here, use the JTAG interface for

prototype download and debugging. Regardless of the configuration mode ultimately

used in the application, it is best to also include a JTAG configuration path for easy design

development. Also see Chapter 3, Boundary-Scan and JTAG Configuration.

• Platform Cable USB II

http://www.xilinx.com/products/devkits/HW-USB-II-G.htm

• Parallel Cable IV

http://www.xilinx.com/products/devkits/HW-PC4.htm

The Basic Configuration Solution

Basic options include either Master Serial mode using a Xilinx Platform Flash PROM or a

third-party SPI PROM. These solutions use the fewest FPGA pins, have flexible I/O

voltage support, and select SPI PROMs are supported by iMPACT, the Xilinx JTAG-based

programming software. See iMPACT Help under Software Help:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/isehelp_start.htm.

X-Ref Target - Figure 1-2

Figure 1-2: Slave Configuration Modes

DIN

CCLK

SERIAL_DATA

CLOCK

Spartan-6 FPGA

Processor,

Microcontroller

TDI

TMS

DATA_OUT

CLOCK

Spartan-6 FPGA

JTAG Tester,

Processor,

Microcontroller

TCK

TDO

MODE_SELECT

DATA_IN

D[7:0]

RDWR_B

CCLK

CSI_B

DATA[7:0]

SELECT

READ/WRITE

CLOCK

Spartan-6

FPGA

Processor,

Microcontroller

(a) Slave Serial Mode

(b) JTAG

UG380_c1_02_051109

Serial SelectMAP

8,16

D[15:8]DATA[15:8]

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UG380 (v2.2) July 30, 2010

Design Considerations

The Low-Cost Priority Solution

The option with the lowest cost varies depending on the specific application.

• If there is spare nonvolatile memory already available in the system, the bitstream

image can be stored in system memory. It can even be stored on a hard drive or

downloaded remotely over a network connection. If so, one of the downloaded

modes should be considered: Slave SelectMAP Mode, Slave Serial Mode, or JTAG.

• If nonvolatile memory is already required for an application, it is possible to

consolidate the memory. For example, the FPGA configuration bitstream(s) can be

stored with any processor code for the board. If the processor is a MicroBlaze

™

embedded processor in the FPGA, the FPGA configuration data and the MicroBlaze

processor code can share the same nonvolatile memory device.

• Spartan-6 FPGAs optionally configure directly from commodity SPI serial flash and

parallel NOR flash memories. See Chapter 2, Configuration Interface Basics. Also see

XAPP973

, Indirect Programming of BPI PROMs with Virtex-5 FPGAs, and XAPP974,

Indirect Programming of SPI Serial Flash PROMs with Spartan-3A FPGAs.

The High-Speed Priority Option

Some applications require the logic to be operational within a short time. Certain FPGA

configuration modes and methods are faster than others. The configuration time includes

the initialization time plus the configuration time. Configuration time depends on the size

of the device and speed of the configuration logic. For example, configuring at 33 MHz

with a 4-bit data bus, a Spartan-6 XC6SLX16 FPGA requires ~28 ms to receive its 3.6 Mb of

configuration data.

• At the same clock frequency, parallel configuration modes are inherently faster than

the serial modes because they program multiple bits at a time.

• Configuring a single FPGA is inherently faster than configuring multiple FPGAs in a

daisy-chain. In a multi-FPGA design where configuration speed is a concern, each

FPGA should be configured separately and in parallel.

• In Master modes, the FPGA internally generates the CCLK configuration clock signal.

By default, the CCLK frequency starts out low but can be increased using the

ConfigRate bitstream option. The maximum supported CCLK frequency setting

depends on the read specifications for the attached nonvolatile memory. A faster

memory enables faster configuration. The FPGA's CCLK output frequency varies

with process, voltage, and temperature. The fastest guaranteed configuration rate

depends on the slowest guaranteed CCLK frequency, as shown in the Spartan-6 FPGA

data sheet. If an external clock is available on the board, it is also possible to configure

the FPGA in Slave mode while using Xilinx Platform Flash.

• If an external clock is available on the board, the FPGA supports the ability to connect

and use an external clock source during Master mode configuration. It is also possible

to use an external clock source to configure the FPGA in a slave mode while using

Xilinx Platform Flash. The external clock source during configuration enables

predictable configuration times to be achieved in Master modes as well as Slave

modes.

Conforming to PCI Link Activation Requirements

The PCI™ Local Bus Specification, Revision 3.0 (“the PCI specification”) defines a number

of power and reset requirements. These requirements, when considered in an FPGA

implementation, create several challenges that must be addressed for long term reliability

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Chapter 1: Configuration Overview

and broad interoperability. It is important to consider the link activation time in the PCI

application and ensure the FPGA can complete configuration during the specified time.

Many third-party flash vendors do not meet these specific time constraints.

Single and Multiple Configuration Images

In most FPGA applications, the FPGA is loaded only when the system is powered on.

However, some applications reload the FPGA multiple times while the system is

operating, with different FPGA bitstreams for different functions. For example, the FPGA

can be loaded with one bitstream to implement a power-on self-test, followed by a second

bitstream with the final application. In many test equipment applications, the FPGA is

loaded with different bitstreams to execute hardware-assisted tests. In this way, one

smaller FPGA can implement the equivalent functionality of a larger ASIC or gate array

device.

See Chapter 7, Reconfiguration and MultiBoot, for more information.

MultiBoot /Safe Update

In advanced applications, multiple bitstream images can be stored. One of the images can

be upgraded by the user application, and real-time system upgrades can occur. The system

can also recover from any failure booting from the initial image.

Required I/O Voltages

The chosen FPGA configuration mode places some constraints on the FPGA application,

specifically the I/O voltage allowed on the FPGA's configuration banks.

For example, the SPI or BPI modes leverage third-party flash memory components that are

usually 3.3V-only devices (but tolerant to lower voltages). This requires that the I/O

voltage on the bank or banks attached to the memory must comply with the input voltage.

Nonvolatile Data Storage

Some FPGA applications store data in external nonvolatile memory. Spartan-6 FPGAs

provide useful enhancements for these applications.

• Spartan-6 FPGAs can configure directly from external commodity serial (SPI) or

parallel Flash PROMs (BPI).

• The Flash PROM address, data, and control pins are only borrowed by the FPGA

during configuration. After configuration, the FPGA has full read/write control over

these pins.

• The FPGA configuration bitstreams and the application’s nonvolatile data can share

the same PROM, reducing overall system cost.

FPGA Density Migration

The package footprint and pinouts for Spartan-6 FPGAs are designed to allow migration

between different densities within a specific family.

Likewise, an FPGA application can store other nonvolatile data in the flash memory,

requiring a larger storage device.

Spartan-6 FPGA Configuration User Guide www.xilinx.com 19

UG380 (v2.2) July 30, 2010

Design Considerations

To support design migration between device densities, sufficient configuration memory

must be allowed to cover the largest device in the targeted package. For example, if using

the Spartan-6 XC6SLX9 device, enough configuration memory to accommodate 2.6 Mb is

required. To allow for migration to the Spartan-6 XC6SLX16 device, 3.6 Mb of

configuration memory is required.

In downloaded applications, enough space in the memory must be reserved for the largest

anticipated, uncompressed FPGA bitstream.

In self-loaded applications, a PROM footprint and the associated FPGA configuration

mode should be used to facilitate easy migration. For example, Xilinx Platform Flash

provides excellent migration between 1 to 4 Mb using the XCFxxS serial family and

between 8 to 32 Mb using the XCFxxP parallel family. If an application spans between the

two, two separate footprints should be used, one for each Platform Flash subfamily. The

XCFxxP Flash family requires a 1.8V core supply voltage input while the XCFxxS requires

3.3V. Both families provide 3.3V I/O.

The SPI serial flash vendors offer a wider migration range but do require a multi-package

footprint. For example, the Atmel DataFlash SPI serial flash family spans the range of

1to64Mb, using a single footprint that accommodates the JEDEC and EIAJ versions of the

8-pin SOIC package along with the 8-connector CASON package. The Numonyx SPI serial

flash has uses a different footprint that uses a combined 8-pin and 16-pin SOIC footprint

and is also compatible with devices from multiple SPI flash vendors.

Similarly, parallel flash supports a wide density range in a common, multi-vendor package

footprint. This overview is provided as an example; flash vendors should be consulted for

specific details.

Production Lifetime

An application’s production lifetime should be considered. Commodity memories

generally have a shorter production lifetime than the proprietary Xilinx Platform Flash

PROMs. For example, if an industrial application is built that will be manufactured for five

years or more, Xilinx Platform Flash PROMs provide better long-term availability.

Products with shorter production lifetimes can benefit from the multi-vendor pricing and

multi-sourcing of commodity memories.

Protecting the FPGA Bitstream against Unauthorized Duplication

Like processor code, the bitstream that defines the FPGA’s functionality loads into the

FPGA during power-on. Consequently, this means that an unscrupulous company can

capture the bitstream and create an unauthorized copy of the design.

Like processors, there are multiple techniques to protect the FPGA bitstream and any

intellectual property (IP) cores embedded in the FPGA. One of the most powerful

techniques is called authentication, which uses unique device “DNA,” and is described in

more detail in Chapter 5, Configuration Details. In addition, the XC6SLX75/T,

XC6SLX100/T, and XC6SLX150/T devices also have on-chip Advanced Encryption

Standard (AES) decryption logic to provide a high degree of design security.

Loading Multiple FPGAs with the Same Configuration Bitstream

Generally, there is one configuration bitstream image per FPGA in a system. Multiple,

different FPGA bitstream images can share a single configuration PROM by leveraging a

configuration daisy-chain. However, if all the FPGAs in the application have the same part

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