JEDEC Standard No. 21-C, Release 30
Page 4.1.2.L-6 – 16
8.1.10 Byte 9 (0x009): Other SDRAM Optional Features
This byte, shown in Table 24, defines support for certain SDRAM features. This value comes from the DDR4 SDRAM data sheet.
8.1.11 Byte 10 (0x00A): Secondary SDRAM Package Type
For modules having asymmetrical assembly of multiple SDRAM package types, this byte, shown in Table 25, defines the secondary
set of SDRAMs. For modules with symmetrical assembly, this byte must be coded as 0x00.
DRAM Density Ratio Settings (Table 26):
8.1.12 Byte 11 (0x00B): Module Nominal Voltage, VDD
This byte, shown in Table 27, describes the Voltage Level for DRAM and other components on the module such as the register or
memory buffer if applicable. Note that SPDs or thermal sensor components are on the VDDSPD supply and are not affected by this
byte.
Table 24 — Byte 9 (0x009): Other SDRAM Optional Features
Bits 7~6 Bit 5 Bit 4 Bits 3~0
Post Package Repair (PPR) Soft PPR MBIST PPR Reserved
00: PPR not supported
01: Post package repair supported,
one row per bank group
10: Reserved
11: Reserved
0 = Soft PPR not supported
1 = Soft PPR supported
0 = MBIST PPR not supported
1 = MBIST PPR supported
Reserved; must
be coded as 0000
NOTE If PPR is supported, Hard PPR is always supported by the device. Optional additional support for Soft PPR is
indicated in bit 5.
Table 25 — Byte 10 (0x00A): Secondary SDRAM Package Type
Bit 7 Bits 6~4 Bits 3~2 Bits 1~0
SDRAM Package Type Die Count
DRAM Density Ratio
1
Signal Loading
0 = Monolithic DRAM Device
1 = Non-Monolithic Device
1
000 = Single die
001 = 2 die
010 = 3 die
011 = 4 die
100 = 5 die
101 = 6 die
110 = 7 die
111 = 8 die
00 = Rank 1 and 3 device densities are
the same as rank 0 and 2 densities
01 = Rank 1 and 3 are one standard
device density smaller than rank 0 and 2
10 = Rank 1 and 3 are two standard
device densities smaller than rank 0 and
2
11 = Reserved
00 = Not specified
01 = Multi load stack
10 = Single load stack (3DS)
11 = Reserved
NOTE 1 When DRAM Density Ratio (bits 3~2) is non-zero, all SPD settings except timing parameters are specified for
the higher density devices in rank 0 (e.g., density, row, column, etc.). SPD timing parameters are specified for the slowest
device timings of any rank (e.g., tCK, tAA, tRFC, etc.).
NOTE 2 See Byte 6 for packaging notes.
Table 26 — DRAM Density Ratio Settings
SPD Byte 4,
Bits 3~0
Ranks 0, 2
Device Density
SPD Byte 10,
Bits 3~2
Ranks 1, 3
Device Density
SPD Byte 10,
Bits 3~2
Ranks 1, 3
Device Density
0000 256 Mb 01 Not Defined 10 Not Defined
0001 512 Mb 01 256 Mb 10 Not Defined
0010 1 Gb 01 512 Mb 10 256 Mb
0011 2 Gb 01 1 Gb 10 512 Mb
0100 4 Gb 01 2 Gb 10 1 Gb
0101 8 Gb 01 4 Gb 10 2 Gb
0110 16 Gb 01 12 Gb 10 8 Gb
0111 32 Gb 01 24 Gb 10 16 Gb
1000 12 Gb 01 8 Gb 10 4 Gb
1001 24 Gb 01 16 Gb 10 12 Gb
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