"DDR4 SPD 标准协议：优化内存通道初始化与优化的关键信息"

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DDR4 SPD标准协议描述了所有DDR4内存模块的串行存在检测（SPD）值。SPD数据提供了有关内存通道上所有模块的关键信息，并旨在由系统的BIOS使用，以便正确地初始化和优化系统内存通道。为了允许最大的灵活性随着设备的发展，本文档中描述的SPD字段可能支持设备配置和不包括在JEDEC DDR4 SDRAM数据表（JESD79-4）中的计时选项。此外，由于SPD EEPROM的存储容量有限，因此采用了多种技术进行优化这些字节的使用，包括覆盖和运行长度有限的编码。根据JEDEC标准21-C，发布30页4.1.2.L-6 - 1，JESD 21-C章节标题：L附录：DDR4 SDRAM模块的串行存在检测（SPD）委员会文件参考标题：DDR4 SPD文件发布6，设备类型标识符UDIMM修订1.3，RDIMM修订1.4，LRDIMM修订1.5，NVDIMM-N修订1.3。串行存在检测（SPD）是一种重要的协议，用于描述DDR4内存模块的信息。SPD值包括设备类型标识符、修订版本以及其他关键信息，以确保系统能够正确地识别和初始化内存模块。此外，SPD还提供了关于内存通道上所有模块的详细信息，以帮助系统BIOS正确优化内存通道。由于SPD EEPROM的存储容量有限，因此需要采用多种优化技术来节省空间。其中包括覆盖和运行长度有限的编码，以确保在有限的存储空间内存储尽可能多的关键信息。这些优化技术使得SPD数据能够在占用较少的存储空间的同时仍提供必要的关键信息。此外，为了允许最大的灵活性，SPD字段可能支持设备配置和不包括在JEDEC DDR4 SDRAM数据表（JESD79-4）中的计时选项。这意味着DDR4内存模块可能具有各种配置和计时选项，而这些选项可能不在标准数据表中列出，因此需要通过DRAM供应商资料表或JESD79-4来确定组件的兼容性。总之，DDR4 SPD标准协议对所有DDR4内存模块的串行存在检测（SPD）值进行了详细描述，提供了关键的信息以帮助系统正确初始化和优化内存通道。通过优化存储空间和支持设备配置和计时选项，SPD协议为DDR4内存模块的灵活性和兼容性提供了重要保障。

JEDEC Standard No. 21-C, Release 30

Page 4.1.2.L-6 – 14

8.1.5 Byte 4 (0x004): SDRAM Density and Banks (Cont’d)

8.1.6 Byte 5 (0x005): SDRAM Addressing

This byte, shown in Table 19, describes the row addressing and the column addressing in the SDRAM device. Bits 2~0 encode the

number of column address bits, and bits 5~3 encode the number of row address bits. These values come from the DDR4 SDRAM

data sheet.

8.1.7 Byte 6 (0x006): Primary SDRAM Package Type

This byte, shown in Table 20, describes the type of SDRAM devices on the module. For modules having asymmetrical assembly of

multiple SDRAM package types, this byte defines the primary set of SDRAMs; Byte 10 defines the secondary set.

Table 18 — Byte 4 (0x004): SDRAM Density and Banks

Bits 7~6 Bits 5~4 Bits 3~0

Bank Group Bits

Bank Address Bits

Total SDRAM capacity per die,

in megabits

Bits [7, 6]:

00 = 0 (no bank groups)

01 = 1 (2 bank groups)

10 = 2 (4 bank groups)

11 = reserved

Bit [5, 4] :

00 = 2 (4 banks)

01 = 3 (8 banks)

All others reserved

Bit [3, 2, 1, 0] :

0000 = 256 Mb

0001 = 512 Mb

0010 = 1 Gb

0011 = 2 Gb

0100 = 4 Gb

0101 = 8 Gb

0110 = 16 Gb

0111 = 32 Gb

1000 = 12 Gb

1001 = 24 Gb

All others reserved

NOTE 1 Bank Address Bits determine the number of banks in each Bank Group.

Table 19 — Byte 5 (0x005): SDRAM Addressing

Bits 7~6 Bits 5~3 Bits 2~0

Reserved Row Address Bits Column Address Bits

Reserved; must be coded as 00 Bit [5, 4, 3] :

000 = 12

001 = 13

010 = 14

011 = 15

100 = 16

101 = 17

110 = 18

All others reserved

Bit [2, 1, 0] :

000 = 9

001 = 10

010 = 11

011 = 12

All others reserved

Table 20 — Byte 6 (0x006): Primary SDRAM Package Type

Bit 7 Bits 6~4 Bits 3~2 Bit 1~0

Primary SDRAM Package Type Die Count Reserved

Signal Loading

0 = Monolithic DRAM Device

1 = Non-Monolithic Device

000 = Single die

001 = 2 die

010 = 3 die

011 = 4 die

100 = 5 die

101 = 6 die

110 = 7 die

111 = 8 die

00 = Not specified

01 = Multi load stack

10 = Single load stack (3DS)

11 = Reserved

NOTE 1 This includes Dual Die, Quad Die, Multi-Die, 3DS, or physically stacked devices - anything that is outside the

standard monolithic device.

NOTE 2 Refers to loading on signals at the SDRAM balls. Loading on certain signals (CKE, ODT, etc.) per specification

of device stacking as defined in JESD79-4.

NOTE 3 Monolithic DRAM device coded as 00 in bits 1~0.

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JEDEC Standard No. 21-C, Release 30

Page 4.1.2.L-6 – 15

8.1.7 Byte 6 (0x006): Primary SDRAM Package Type (Cont’d)

Terminology (Table 21):

8.1.8 Byte 7 (0x007): SDRAM Optional Features

This byte, shown in Table 22, defines support for certain SDRAM features. This value comes from the DDR4 SDRAM data sheet.

8.1.9 Byte 8 (0x008): SDRAM Thermal and Refresh Options

This byte, shown in Table 23, describes the module’s supported operating temperature ranges and refresh options. These values come

from the DDR4 SDRAM data sheet. Please refer to the DDR4 SDRAM data sheet (JESD79-4 or supplier data sheet) for a complete

description of these options.

Table 21 — Package Type Terminology

SDRAM

Package

Type

Abbre-

viation

Description

# Electrical Loads ...

... On data,

mask, and

strobe signals

... On address

and command

signals

... On control

signals

except CKE

... On CKE

signals

Monolithic SDP Single die package 1 1 1 1

Multi-load

stack

DDP Dual Die Package 2 2 1 1

QDP Quad Die Package 4 4 1 2

Single load

stack

2H 3DS

Two SDRAM die

single load stack

1 1 1 1

3H 3DS

Three SDRAM die

single load stack

1 1 1 1

4H 3DS

Four SDRAM die

single load stack

1 1 1 1

5H 3DS

Five SDRAM die

single load stack

1 1 1 1

6H 3DS

Six SDRAM die

single load stack

1 1 1 1

7H 3DS

Seven SDRAM die

single load stack

1 1 1 1

8H 3DS

Eight SDRAM die

single load stack

1 1 1 1

Table 22 — Byte 7 (0x007): SDRAM Optional Features

Bits 7~6 Bits 5~4 Bits 3~0

Reserved

Maximum Activate

Window (tMAW)

Maximum Activate Count (MAC)

Reserved; must be coded as 00 Bits [5, 4]:

00 = 8192 * tREFI

01 = 4096 * tREFI

10 = 2048 * tREFI

11 = Reserved

Bits [3, 2, 1, 0] :

0000 = Untested MAC

0001 = 700 K

0010 = 600 K

0011 = 500 K

0100 = 400 K

0101 = 300 K

0110 = 200 K

0111 = Reserved

1000 = Unlimited MAC

All others reserved

NOTE 1 Untested MAC means the device is not tested for tMAW and/or MAC; no particular value should be assumed.

NOTE 2 Unlimited MAC means there is no restriction to the number of activates to a given row in a refresh period

providing DRAM timing requirements such as tRCmin and refresh requirements are not violated.

Table 23 — Byte 8 (0x008): SDRAM Thermal and Refresh Options

Bits 7~0

Reserved

Reserved; must be coded as 0x00

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JEDEC Standard No. 21-C, Release 30

Page 4.1.2.L-6 – 16

8.1.10 Byte 9 (0x009): Other SDRAM Optional Features

This byte, shown in Table 24, defines support for certain SDRAM features. This value comes from the DDR4 SDRAM data sheet.

8.1.11 Byte 10 (0x00A): Secondary SDRAM Package Type

For modules having asymmetrical assembly of multiple SDRAM package types, this byte, shown in Table 25, defines the secondary

set of SDRAMs. For modules with symmetrical assembly, this byte must be coded as 0x00.

DRAM Density Ratio Settings (Table 26):

8.1.12 Byte 11 (0x00B): Module Nominal Voltage, VDD

This byte, shown in Table 27, describes the Voltage Level for DRAM and other components on the module such as the register or

memory buffer if applicable. Note that SPDs or thermal sensor components are on the VDDSPD supply and are not affected by this

byte.

Table 24 — Byte 9 (0x009): Other SDRAM Optional Features

Bits 7~6 Bit 5 Bit 4 Bits 3~0

Post Package Repair (PPR) Soft PPR MBIST PPR Reserved

00: PPR not supported

01: Post package repair supported,

one row per bank group

10: Reserved

11: Reserved

0 = Soft PPR not supported

1 = Soft PPR supported

0 = MBIST PPR not supported

1 = MBIST PPR supported

Reserved; must

be coded as 0000

NOTE If PPR is supported, Hard PPR is always supported by the device. Optional additional support for Soft PPR is

indicated in bit 5.

Table 25 — Byte 10 (0x00A): Secondary SDRAM Package Type

Bit 7 Bits 6~4 Bits 3~2 Bits 1~0

SDRAM Package Type Die Count

DRAM Density Ratio

Signal Loading

0 = Monolithic DRAM Device

1 = Non-Monolithic Device

000 = Single die

001 = 2 die

010 = 3 die

011 = 4 die

100 = 5 die

101 = 6 die

110 = 7 die

111 = 8 die

00 = Rank 1 and 3 device densities are

the same as rank 0 and 2 densities

01 = Rank 1 and 3 are one standard

device density smaller than rank 0 and 2

10 = Rank 1 and 3 are two standard

device densities smaller than rank 0 and

11 = Reserved

00 = Not specified

01 = Multi load stack

10 = Single load stack (3DS)

11 = Reserved

NOTE 1 When DRAM Density Ratio (bits 3~2) is non-zero, all SPD settings except timing parameters are specified for

the higher density devices in rank 0 (e.g., density, row, column, etc.). SPD timing parameters are specified for the slowest

device timings of any rank (e.g., tCK, tAA, tRFC, etc.).

NOTE 2 See Byte 6 for packaging notes.

Table 26 — DRAM Density Ratio Settings

SPD Byte 4,

Bits 3~0

Ranks 0, 2

Device Density

SPD Byte 10,

Bits 3~2

Ranks 1, 3

Device Density

SPD Byte 10,

Bits 3~2

Ranks 1, 3

Device Density

0000 256 Mb 01 Not Defined 10 Not Defined

0001 512 Mb 01 256 Mb 10 Not Defined

0010 1 Gb 01 512 Mb 10 256 Mb

0011 2 Gb 01 1 Gb 10 512 Mb

0100 4 Gb 01 2 Gb 10 1 Gb

0101 8 Gb 01 4 Gb 10 2 Gb

0110 16 Gb 01 12 Gb 10 8 Gb

0111 32 Gb 01 24 Gb 10 16 Gb

1000 12 Gb 01 8 Gb 10 4 Gb

1001 24 Gb 01 16 Gb 10 12 Gb

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JEDEC Standard No. 21-C, Release 30

Page 4.1.2.L-6 – 17

8.1.12 Byte 11 (0x00B): Module Nominal Voltage, VDD (Cont’d)

'Operable' is defined as the VDD voltage at which module operation is allowed using the performance values programmed in the

SPD.

'Endurant' is defined as the VDD voltage at which the module may be powered without adversely affecting the life expectancy or

reliability. Operation is not supported at this voltage.

Examples:

A value on bits 1~0 of 11 defines DRAM support of a nominal operable voltage of 1.2 V only.

8.1.13 Byte 12 (0x00C): Module Organization

This byte, shown in Table 28, describes the organization of the SDRAM module. Bits 2~0 encode the device width of the SDRAM

devices. Bits 5~3 encode the number of package ranks on the module.

“Package ranks per DIMM” refers to the collections of devices on the module sharing common chip select signals (across the data

width of the DIMM), either from the edge connector for unbuffered modules or from the outputs of a registering clock driver for

RDIMMs and LRDIMMs.

“Logical rank” refers the individually addressable die in a 3DS stack and has no meaning for monolithic or multi-load stacked

SDRAMs, however, for the purposes of calculating the capacity of the module, one should treat monolithic and multi-load stack

SDRAMs as having one logical rank per package rank.

Symmetrical Configurations

Byte 12 Bit 6 = 0 defines a memory module as being “symmetrical” where all DRAM devices on the module are the same type as

described in Byte 6.

Symmetrical configurations are shown in Figure 1 and Table 29.

Table 27 — Byte 11: Module Nominal Voltage, VDD

Reserved DRAM VDD 1.2 V

Bits 7~2 Bit 1 Bit 0

Reserved;

must be coded as 000000

0 = not endurant

1 = endurant

0 = not operable

1 = operable

Table 28 — Byte 12 (0x00C): Module Organization

Bit 7 Bit 6 Bits 5~3 Bits 2~0

Reserved Rank Mix Number of Package Ranks per DIMM SDRAM Device Width

Reserved; must

be coded as 0

0 = Symmetrical

1 = Asymmetrical

Bit [5, 4, 3] :

000 = 1 Package Rank

001 = 2 Package Ranks

010 = 3 Package Ranks

011 = 4 Package Ranks

100 = 5 Package Ranks

101 = 6 Package Ranks

110 = 7 Package Ranks

111 = 8 Package Ranks

Bit [2, 1, 0] :

000 = 4 bits

001 = 8 bits

010 = 16 bits

011 = 32 bits

All others reserved

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