SC16IS752IPW：I2C/SPI到UART转换器，高性能通信解决方案

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"SC16IS752IPW 是一款集成了I2C总线/SPI总线接口的双通道高性能UART（通用异步收发传输器），它提供了高达5Mbit/s的数据速率，同时具有低运行电流和睡眠电流，适合于手持式和电池供电的应用。该器件采用超小型的HVQFN32和TSSOP28封装。SC16IS752IPW芯片实现了无缝的I2C/SPI到RS-232/RS-485协议转换，并且是完全双向的。SC16IS762与SC16IS752的主要区别在于，SC16IS762支持SPI时钟速度高达15Mbit/s，而SC16IS752支持4Mbit/s，以及SC16IS762支持IrDA SIR速度可达1.152Mbit/s。在其他方面，两者在功能和电气特性上相同。这两款芯片的内部寄存器集与广泛使用的16C450兼容，这意味着软件编写或从其他平台移植都非常方便。此外，SC16IS752IPW还提供了诸如硬件和软件流控制、自动RS-485支持等高级功能。" 这篇摘要主要涵盖了以下知识点： 1. **SC16IS752IPW**：这是由Silicon Labs制造的一款集成电路，用于实现微控制器与串行通信接口之间的接口，特别是I2C和SPI总线到RS-232/RS-485的转换。 2. **双通道高性能UART**：SC16IS752IPW提供两个独立的UART通道，每个通道都能处理高速数据传输，最大速率可达5Mbit/s，适用于需要高速串行通信的场合。 3. **低功耗设计**：该器件在运行和待机模式下都具有低电流消耗特性，这使其特别适合电池供电的便携设备。 4. **封装形式**：SC16IS752IPW采用HVQFN32和TSSOP28两种封装，这两种封装尺寸小，有利于减少电路板空间。 5. **协议转换**：芯片能够实现I2C/SPI与RS-232/RS-485协议间的无缝转换，这使得在不同通信标准之间切换变得简单。 6. **双向通信**：该芯片支持全双工通信，即在同一时刻既能发送也能接收数据。 7. **SC16IS762的区别**：相比于SC16IS752，SC16IS762的SPI时钟速度更快，达到15Mbit/s，以及支持红外数据协会（IrDA）的SIR模式，速度可达1.152Mbit/s。 8. **软件兼容性**：内部寄存器集与16C450兼容，意味着软件开发可以基于已有的16C450经验，降低了软件开发的难度和时间成本。 9. **高级特性**：包括硬件和软件流控制，这有助于管理和优化数据传输速率，防止数据溢出；自动RS-485支持则简化了多点通信网络的配置。这些知识点对于理解SC16IS752IPW的功能、应用领域以及如何在系统设计中使用该芯片至关重要。在实际应用中，这些特性使得SC16IS752IPW成为需要高效、低功耗串行通信解决方案的理想选择。

Product data sheet Rev. 06 — 19 December 2006 10 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.2.2 Auto-CTS

Figure 6 shows CTS functional timing. The transmitter circuitry checks CTS before

sending the next data character. When CTS is active, the transmitter sends the next

character. To stop the transmitter from sending the following character, CTS must be

deasserted before the middle of the last stop bit that is currently being sent. The

Auto-CTS function reduces interrupts to the host system. When ﬂow control is enabled,

CTS level changes do not trigger host interrupts because the device automatically

controls its own transmitter. Without Auto-CTS, the transmitter sends any data present in

the transmit FIFO and a receiver overrun error may result.

7.3 Software ﬂow control

Software ﬂow control is enabled through the Enhanced Features Register and the Modem

Control Register. Different combinations of software ﬂow control can be enabled by setting

different combinations of EFR[3:0]. Table 3 shows software ﬂow control options.

(1) When CTS is LOW, the transmitter keeps sending serial data out.

(2) When CTS goes HIGH before the middle of the last stop bit of the current character, the transmitter ﬁnishes sending the

current character, but it does not send the next character.

(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.

Fig 6. CTS functional timing

start bit 0 to bit 7 stopTX

CTS

002aab041

start stop

bit 0 to bit 7

Table 3. Software ﬂow control options (EFR[3:0])

EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software ﬂow control

0 0 X X no transmit ﬂow control

1 0 X X transmit Xon1, Xoff1

0 1 X X transmit Xon2, Xoff2

1 1 X X transmit Xon1 and Xon2, Xoff1 and Xoff2

X X 0 0 no receive ﬂow control

X X 1 0 receiver compares Xon1, Xoff1

X X 0 1 receiver compares Xon2, Xoff2

1011transmit Xon1, Xoff1

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0111transmit Xon2, Xoff2

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

1111transmit Xon1 and Xon2, Xoff1 and Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

0011no transmit ﬂow control

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Product data sheet Rev. 06 — 19 December 2006 11 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

There are two other enhanced features relating to software ﬂow control:

• Xon Any function (MCR[5]): Receiving any character will resume operation after

recognizing the Xoff character. It is possible that an Xon1 character is recognized as

an Xon Any character, which could cause an Xon2 character to be written to the

RX FIFO.

• Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the

special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The

Xoff interrupt is cleared by a read of the Interrupt Identiﬁcation Register (IIR). The

special character is transferred to the RX FIFO.

7.3.1 Receive ﬂow control

When software ﬂow control operation is enabled, the SC16IS752/SC16IS762 will

compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1

and Xoff2 must be received sequentially). When the correct Xoff characters are received,

transmission is halted after completing transmission of the current character. Xoff

detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ to go LOW.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases

Xon1 and Xon2 must be received sequentially). When the correct Xon characters are

received, IIR[4] is cleared, and the Xoff interrupt disappears.

7.3.2 Transmit ﬂow control

Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the halt trigger level

programmed in TCR[3:0], or the selectable trigger level in FCR[7:6].

Xon1/Xon2 character is transmitted when the RX FIFO reaches the resume trigger level

programmed in TCR[7:4], or falls below the lower selectable trigger level in FCR[7:6].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an

ordinary character from the FIFO. This means that even if the word length is set to be 5, 6,

or 7 bits, then the 5, 6, or 7 least signiﬁcant bits of Xoff1/Xoff2, Xon1/Xon2 will be

transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but

this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software ﬂow control and hardware ﬂow control will never be enabled

simultaneously. Figure 7 shows an example of software ﬂow control.

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