2017年IEEE UVM语言参考手册：通用验证方法论标准

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IEEE 1800.2™-2017《通用验证方法学语言参考手册》是由设计自动化标准委员会（Design Automation Standards Committee, DAC）赞助并由IEEE计算机学会发布的标准化文档。该手册是针对电子设计自动化领域中的一种通用验证方法论，旨在提供一种统一的语言和框架，以支持软件和硬件交互的系统级验证。该标准手册的主要目标是定义和规范通用验证方法学语言（Universal Verification Methodology, UVM），这是一种被广泛应用于半导体验证领域的高级抽象层语言。UVM允许测试工程师在验证环境中组织和管理复杂的测试流程，通过模块化、层次化的设计，提高了测试的可维护性和重复性。UVM包括了环境（Environment）、接口适配器（Adapter）、接口（Interface）、模型（Model）和测试库（Test Library）等关键组件，它们共同构建了一个完整的验证体系结构。 IEEE 1800.2™-2017不仅详细阐述了UVM的语法和语义，还提供了如何在实际项目中有效使用UVM的最佳实践和指导原则。它涵盖了测试套件的创建、配置管理、覆盖率分析、故障注入、以及与仿真器、硬件接口的集成等内容。此外，手册还强调了代码风格、命名约定和文档编写的重要性，以确保代码的可读性和一致性。作为一份重要的技术文档，IEEE 1800.2™-2017对验证工程师来说是不可或缺的参考资料。它对于遵循行业最佳实践，提升验证效率，以及减少设计和验证中的错误都具有深远的影响。值得注意的是，这份手册的使用受到限制，仅授权给特定用户David Han，并且下载日期为2019年4月7日，可能涉及版权和使用许可的规定。 IEEE 1800.2™-2017是电子设计验证领域的重要标准，它提供了一种强大的工具集和框架，帮助设计者和测试人员进行高质量的系统级验证，确保电子系统的功能正确性和可靠性。理解和掌握该标准，对于从事半导体或其他相关行业的工程人员来说，是提升职业素养和推动项目成功的关键。

IEEE Std 1800.2-2017

IEEE Standard for Universal Verification Methodology Language Reference Manual

UVM does not require any specific time unit precision for uvm_pkg.

All UVM methods that operate on values of type time, such as uvm_printer::print_time (see 16.2.3.11

are subject to the time scaling defined in IEEE Std 1800™.

1.3.6 Random stability

Any APIs that result in user code being executed are not guaranteed to be random stable. All other APIs are

guaranteed to be random stable, unless otherwise specified.

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IEEE Std 1800.2-2017

IEEE Standard for Universal Verification Methodology Language Reference Manual

2. Normative references

The following referenced documents are indispensable for the application of this standard (i.e., they must be

understood and used, so each referenced document is cited in text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of

the referenced document (including any amendments or corrigenda) applies.

IEEE Std 1800™, IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and

Verification Language.

3. Definitions, acronyms, and abbreviations

For the purposes of this document, the following terms and definitions apply. The IEEE Standards

Dictionary Online should be consulted for terms not defined in this clause.

3.1 Definitions

agent: An abstract container used to emulate and verify device under test (DUT) devices; agents encapsulate

a driver, sequencer, and monitor.

blocking: An interface where tasks block execution until they complete. See also: non-blocking.

component: A piece of verification intellectual property (VIP) that provides functionality and interfaces.

consumer: A verification component that receives transactions from another component.

driver: A component responsible for executing or otherwise processing transactions, usually interacting

with the device under test (DUT) to do so.

environment: The container object that defines the testbench topology.

export: A transaction level modeling (TLM) interface that provides an implementation of methods used for

communication. Used in Universal Verification Methodology (UVM) to connect to a port.

factory method: A classic software design pattern used to create generic code by deferring, until run time,

the exact specification of the object to be created.

hook: A method that enables users to customize certain behaviors of a component.

generator: A verification component that provides transactions to another component. Also referred to as a

producer.

monitor: A passive entity that samples device under test (DUT) signals, but does not drive them.

non-blocking: A call that returns immediately. See also: blocking.

policy: A collection of settings used to apply an operation to a class.

IEEE publications are available from the Institute of Electrical and Electronics Engineers (http://standards.ieee.org/).

The IEEE standards or products referred to in Clause 2 are trademarks owned by the Institute of Electrical and Electronics Engineers,

Incorporated.

IEEE Standards Dictionary Online is available at: http://ieeexplore.ieee.org/.

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IEEE Std 1800.2-2017

IEEE Standard for Universal Verification Methodology Language Reference Manual

port: A transaction level modeling (TLM) interface that defines the set of methods used for communication.

Used in Universal Verification Methodology (UVM) to connect to an export.

proxy: A class functioning as an interface to another component or class.

request: A transaction that provides information to initiate the processing of a particular operation.

response: A transaction that provides information about the completion or status of a particular operation.

scoreboard: The mechanism used to dynamically predict the response of the design and check the observed

response against the predicted response. Usually, refers to the entire dynamic response-checking structure.

sequence: A Universal Verification Methodology (UVM) object that procedurally defines a set of

transactions to be executed and/or controls the execution of other sequences.

sequencer: An advanced stimulus generator that executes sequences that define the transactions provided

to the driver for execution.

singleton: A design pattern where the creation of the class only has one instance of that class.

test: Specific customization of an environment to exercise required functionality of the device under test

(DUT).

testbench: The structural definition of a set of verification components used to verify a device under test

(DUT). Also referred to as a verification environment.

transaction: A class instance that encapsulates information used to communicate between two or more

components.

user: Someone that uses the Universal Verification Methodology (UVM) base class library (BCL).

NOTE—In this standard, user uses the classes, functions, methods, or macros defined herein.

3.2 Acronyms and abbreviations

API application programming interface

BCL base class library

DPI direct programming interface

DUT device under test

EDA electronic design automation

FIFO first-in, first-out

HDL hardware description language

IP intellectual property

RTL register transfer level

TLM transaction level modeling

UVM Universal Verification Methodology

VIP verification intellectual property

Notes in text, tables, and figures are given for information only and do not contain requirements needed to implement the standard.

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IEEE Std 1800.2-2017

IEEE Standard for Universal Verification Methodology Language Reference Manual

4. UVM class reference

The UVM base class library provides the building blocks needed to quickly develop well constructed and

reusable verification components and test environments in SystemVerilog. All UVM API should maintain

random stability.

The UVM classes and utilities are divided into the following categories pertaining to their role or function.

The subsequent clauses of this standard give a more detailed overview of each category—and the classes

that comprise them.

Base—The basic building blocks for all environments are components, which do the actual work,

transactions, which convey information between components, and ports, which provide the interfaces used

to convey transactions. The UVM’s core base classes provide these building blocks. See Clause 5

Reporting—The reporting classes provide a facility for issuing reports (messages) with consistent

formatting and configurable side effects, such as logging to a file or exiting simulation. Reports can also

filter out messages based on their verbosity, unique ID, or severity. See Clause 6

Recording—The recording classes provide a facility to record transactions into a database using a consistent

API. Users can configure what gets sent to the back-end database, without knowing exactly how the

connection to that database is established. See Clause 7

Factory—As the name implies, the UVM factory is used to manufacture (create) UVM objects and

components. A factory can be configured to produce an object of a given type on a global or instance basis.

Factories allow dynamically configurable component hierarchies and object substitutions without having to

modify their code or break encapsulation. See Clause 8

Phasing—This category defines the phasing capability provided by UVM. See Clause 9

Synchronization—These event and barrier synchronization classes can be used for process synchronization.

See Clause 10

Containers—These classes are type parameterized data structures that provide queue and pool services. The

class-based queue and pool types allow for efficient sharing of the data structures compared with their

SystemVerilog built-in counterparts. See Clause 11

UVM TLM—The UVM TLM library defines several abstract, transaction-level interfaces and the ports and

exports that facilitate their use. Each UVM TLM interface consists of one or more methods used to transport

data, typically whole transactions (objects) at a time. Component designs that use UVM TLM ports and

exports to communicate are inherently more reusable, interoperable, and modular. See Clause 12

Components—Components form the foundation of UVM. They encapsulate the behavior of drivers,

scoreboards, and other objects in a testbench. The UVM base class library provides a set of predefined

component types, all derived directly or indirectly from uvm_component. See Clause 13

Sequences—Sequences encapsulate user-defined procedures that generate multiple

uvm_sequence_item-based transactions (see 14.1

). Such sequences can be reused, extended, randomized,

and combined sequentially and hierarchically in interesting ways to produce realistic stimulus to a DUT. See

Clause 14

Sequencers—The sequencer serves as an arbiter for controlling transaction flow from multiple stimulus

generators. More specifically, the sequencer controls the flow of uvm_sequence_item-based transactions

(see 14.1

) generated by one or more uvm_sequence #(REQ,RSP)-based sequences (see 14.3). See

Clause 15

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2017年IEEE UVM语言参考手册：通用验证方法论标准

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