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Data Sheet ADCLK946
Rev. B | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (typ) values are given for V
CC
− V
EE
= 3.3 V and T
A
= 25°C, unless otherwise noted. Minimum (min) and maximum (max) values
are given over the full V
CC
− V
EE
= 3.3 V ± 10% and T
A
= −40°C to +85°C variation, unless otherwise noted.
Table 1. Clock Inputs and Outputs
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC INPUT CHARACTERISTICS
IH
EE
CC
Input Voltage Low Level V
IL
V
EE
V
CC
− 0.2 V
Input Differential Range V
ID
0.4 3.4 V p-p ±1.7 V between input pins
Input Capacitance C
IN
0.4 pF
Input Resistance
Single-Ended Mode 50 Ω
Differential Mode 100 Ω
T
Input Bias Current 20 µA
Hysteresis 10 mV
DC OUTPUT CHARACTERISTICS
Output Voltage High Level V
OH
V
CC
− 1.26 V
CC
− 0.76 V 50 Ω to (V
CC
− 2.0 V)
Output Voltage Low Level V
OL
V
CC
− 1.99 V
CC
− 1.54 V 50 Ω to (V
CC
− 2.0 V)
Output Voltage, Single-Ended V
O
610 960 mV V
OH
− V
OL
, output static
Reference Voltage V
REF
Output Voltage (V
CC
+ 1)/2 V −500 µA to +500 µA
Output Resistance 235 Ω
Table 2. Timing Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC PERFORMANCE
Maximum Output Frequency 4.5 4.8 GHz See Figure 4 for differential output voltage vs.
frequency, >0.8 V differential output swing
Output Rise/Fall Time t
R,
t
F
40 75 90 ps 20% to 80% measured differentially
Propagation Delay t
PD
150 185 220 ps V
ICM
= 2 V, V
ID
= 1.6 V p-p
Temperature Coefficient 50 fs/°C
Output-to-Output Skew 9 28 ps
Part-to-Part Skew
1
45 ps V
ID
= 1.6 V p-p
Additive Time Jitter
Integrated Random Jitter 28 fs rms BW = 12 kHz − 20 MHz, CLK = 1 GHz
Broadband Random Jitter
2
75 fs rms V
ID
= 1.6 V p-p, 8 V/ns, V
ICM
= 2 V
Crosstalk-Induced Jitter
3
90 fs rms
CLOCK OUTPUT PHASE NOISE
Input slew rate > 1 V/ns (see Figure 11 for more details)
f
IN
= 1 GHz −119 dBc/Hz @ 100 Hz offset
−134 dBc/Hz @ 1 kHz offset
−145 dBc/Hz @ 10 kHz offset
−150 dBc/Hz @ 100 kHz offset
−150 dBc/Hz >1 MHz offset
1
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2
Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
3
The amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.
数据表
Rev. B b|第3页,共12页
电特性
除非另有说明,在 V
CC
~V
EE
= 3.3 V和 T
A
= 25°C时给出典型(类型)值。除非另有说明,最小(min)和最大(max)值在整个 V
CC
V
EE
= 3.3 V±1
0%和T
A
=40°C至+85°C变化范围内给出。
表1。时钟输入和输出
测试条件/评论
直流输入特性输入电压高电
平
输入电压低
输入差动范围 输入引脚之间±1.7 V
输入电容
输入电阻单端模式
差模
共模
输入偏置电流
直流输出特性输出电压高电平
至(V
CC
2.0 V)
输出电压低电平
到(V
CC
2.0 V)
输出电压,单端
V
OH
V
OL
,输出静态
参考电压
输出电压 500µA ~ +500µA
输出电阻
表2。时间特征
测试条件/评论
交流性能最大输出频率
差分输出电压与频率的关系见图4,>0.8 V差
分输出摆幅
输出上升/下降时间 20%到80%的测量结果不同
传播延迟
V
ICM
= 2v, V
ID
= 1.6 V p-p
温度系数
Output-to-Output斜
V
ID
= 1.6 V p-p
加性时间抖动集成随机抖
动
fs rms BW = 12khz20mhz, CLK = 1ghz
Jitter
2
fs rms
V
ID
= 1.6 V p-p, 8 V/ns, V
ICM
= 2 V
fs rms
时钟输出相位噪声绝对相位
噪声
输入压摆率> 1 V/ns(参见图11了解更多细节)
f
IN
= 1 GHz
@ 100 Hz偏移
@ 1 kHz偏移
@ 10 kHz偏移
@ 100 kHz偏移
> 1mhz偏移
输出偏差是在相同电压和温度下工作时任意两个相似延迟路径之间的差值。
测量时钟信号的上升沿;采用ADC方法计算信噪比。
当两个相关的异步差分频率应用于输入时,在输出端测量到的增加抖动量。