CUDA编程：GPU并行计算入门指南

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"CUDA编程：开发者指南 - 一本面向GPU并行计算的详细教程，适合对并行计算无经验的读者。本书旨在介绍CUDA，并在并行基础之上深入CUDA安装。书中通过章节分别探讨线程、块、网格、内存等核心概念，既关注并行计算也涵盖CUDA特有的问题。此外，书中的实践示例展示了如何优化应用、适应新硬件以及解决常见问题。内容覆盖多种硬件平台，包括Mac、Linux和Windows系统下的多个NVIDIA芯片组。每章都包含练习题以检验读者的理解程度。" CUDA，全称为Compute Unified Device Architecture，是由NVIDIA推出的并行计算平台和编程模型，允许程序员利用图形处理器（GPU）进行高性能计算。对于初学者来说，CUDA编程提供了进入GPU计算世界的入口。本书“CUDA编程：开发者指南”是为那些对并行计算不熟悉的读者设计的全面教程。首先，书本介绍了CUDA的基础知识，帮助读者理解GPU并行计算的概念。并行计算是一种同时处理多个数据的方法，它可以极大地提高计算效率，尤其在处理大量数据和复杂计算时。GPU因其并行处理能力而被广泛用于科学计算、机器学习、图形渲染等领域。然后，书中详细讲解了CUDA编程环境的搭建，包括安装CUDA软件开发工具包（SDK）。CUDA SDK包含了开发CUDA程序所需的库、头文件和工具，是CUDA编程的基础。接下来，作者深入探讨了CUDA的核心概念： 1. 线程：CUDA线程是执行计算的基本单元，可以理解为在GPU上运行的独立任务。 2. 块：线程组织成块，同一块内的线程可以进行同步操作。 3. 网格：线程块进一步组成网格，网格是线程的顶级组织结构。 4. 内存：CUDA提供了多种内存类型，如全局内存、共享内存、常量内存和纹理内存，每种都有其特定的访问速度和使用场景。书本还教授如何有效地利用这些概念来优化CUDA程序。例如，通过合理的线程配置和内存管理，可以最大化GPU的并行性能。此外，针对不同的硬件平台，书中可能涵盖了如何调整代码以适应不同NVIDIA芯片组的特性，这有助于提升跨平台的兼容性和性能。最后，通过实际案例，书本演示了如何解决CUDA编程中常见的问题，如内存冲突、同步问题以及性能瓶颈。每个章节的练习题则有助于巩固所学知识，让读者能够将理论知识应用于实践中。 “CUDA编程：开发者指南”是一本全面的教材，它不仅讲解了CUDA编程的基本技术，还提供了实践指导和问题解决策略，是初学者和有经验的开发者深入理解并掌握CUDA编程的宝贵资源。

A Short History of Supercomputing

INTRODUCTION

So why in a book about CUDA are we looking at supercomputers? Supercomputers are typically at the

leading edge of the technology curve. What we see here is what will be commonplace on the desktop in

5 to 10 years. In 2010, the annual International Supercomputer Conference in Hamburg, Germany,

announced that a NVIDIA GPU-based machine had been listed as the second most powerful computer

in the world, according to the top 500 list (http://www.top500.org). Theoretically, it had more peak

performance than the mighty IBM Roadrunner, or the then-leader, the Cray Jaguar, peaking at near to 3

petaﬂops of performance. In 2011, NVIDIA CUDA-powered GPUs went on to claim the title of the

fastest supercomputer in the world. It was suddenly clear to everyone that GPUs had arrived in a very

big way on the high-performance computing landscape, as well as the humble desktop PC.

Supercomputing is the driver of many of the technologies we see in modern-day processors.

Thanks to the need for ever-faster processors to process ever-larger datasets, the industry produces

ever-faster computers. It is through som e of these evolutions that GPU CUDA technology has come

about today.

Both supercomputers and desktop computing are moving toward a heterogen eous computing

routedthat is, they are trying to achi eve performance with a mix of CPU (Central Processor Unit) and

GPU (Graphics Processor Unit) technology. Two of the largest worldwide projects using GPUs are

BOINC and Folding@Home, both of which are distributed computing projects. They allow ordinary

people to make a real contri bution to speciﬁc scientiﬁc projects. Contributions from CPU/GPU hosts

on projects supporting GPU accelerators hugely outweigh contributions from CPU-only hosts. As of

November 2011, there were some 5.5 million hosts contributing a total of around 5.3 petaﬂops, around

half that of the world’s fastest supercompute r, in 2011, the Fujitsu “K computer” in Japan .

The replacement for Jaguar, currently the fastest U.S. supercomputer, code-named Titan, is

planned for 2013. It will use almost 300,000 CPU cores and up to 18,000 GPU boards to achieve

between 10 and 20 petaﬂops per second of performance. With support like this from around the world,

GPU programming is set to jump into the mainstream, both in the HPC industry and also on the

desktop.

You can now put together or purch ase a desktop supercomputer with several teraﬂops of perfor-

mance. At the beginning of 2000, some 12 years ago, this would have given you ﬁrst place in the top

500 list, beating IBM ASCI Red with its 9632 Pentium processors. This just shows how much a little

over a decade of computing progress has achieved and opens up the question about where we will be

a decade from now. You can be fairly certain GPUs will be at the forefront of this trend for some time

CHAPTER

CUDA Programming. http://dx.doi.org/10.1016/B978-0-12-415933-4.00001-6

to come. Thus, learning how to program GPUs effectively is a key skill any good developer needs

to acquire.

VON NEUMANN ARCHITECTURE

Almost all processors work on the basis of the process developed by Von Neumann, considered one of

the fathers of computing. In this approach, the processor fetches instructions from memory, decodes,

and then executes that instruction.

A modern processor typically runs at anything up to 4 GHz in speed. Modern DDR-3 memory, when

paired with say a standard Intel I7 device, can run at anything up to 2 GHz. However, the I7 has at least four

processors or cores in one device, or double that if you count its hyperthreading ability as a real processor.

A DDR-3 triple-channel memory setup on a I7 Nehalem system would produce the theoretical

bandwidth ﬁgures shown in Table 1.1. Depending on the motherboard, and exact memory patter n, the

actual bandwidth could be considerably less.

You run into the ﬁrst problem with memory bandwidth when you consi der the processor clock

speed. If you take a processor running at 4 GHz, you need to potentially fetch, every cycle, an

instruction (an operator) plus some data (an operand).

Each instruction is typically 32 bits, so if you execute nothing but a set of linear instructions, with no

data, on every core, you get 4.8 GB/s O 4 ¼ 1.2 GB instructions per second. This assumes the processor

can dispatch one instruction per clock on average*. However, you typically also need to fetch and write

back data, which if we say is on a 1:1 ratio with instructions, means we effectively halve our throughput.

The ratio of clock speed to memory is an important limiter for both CPU and GPU throughput and

something we’ll look at later. We ﬁnd when you look into it, most applications, with a few exceptions on

both CPU and GPU, are often memory bound and not processor cycle or processor clock/load bound.

CPU vendors try to solve this problem by using cache memory and burst memory access. This

exploits the principle of locality. It you look at a typical C program, you might see the following type of

operation in a function:

void some_function

{

int array[100];

int i ¼ 0;

Table 1.1 Bandwidth on I7 Nehalem Processor

QPI Clock Theoretical Bandwidth Per Core

4.8 GT/s

(standard part)

19.2 GB/s 4.8 GB/s

6.4 GT/s

(extreme edition)

25.6 GB/s 6.4 GB/s

Note: QPI ¼ Quick Path Interconnect.

The actual achieved dispatch rate can be higher or lower than one, which we use here for simplicity.

2 CHAPTER 1 A Short History of Supercomputing

If the data is not in the ﬁrst level (L1) cache, then a fetch from the second or third level (L2 or L3)

cache is required, or from the main memory if no cache line has this data already. The ﬁrst level cache

typically runs at or near the processor clock speed, so for the execution of our loop, potentially we do

get near the full processor speed, assuming we write cache as well as read cache. However, there is

a cost for this: The size of the L1 cache is typically only 16 K or 32 K in size. The L2 cache is

somewhat slower, but much larger, typically around 256 K. The L3 cache is much larger, usually

several megabytes in size, but again much slower than the L2 cache.

With real-life examples, the loop iterations are much, much larger, maybe many megabytes in size.

Even if the program can remain in cache memory, the dataset usually cannot, so the processor, despite

all this cache trickery, is quite often limited by the memory throughput or bandwidth.

When the processor fetches an instruction or data item from the cache instead of the main memory,

it’s called a cache hit. The increm ental beneﬁt of using progressively larger caches drops off quite

rapidly. This in turn means the ever-larger caches we see on modern processors are a less and less

useful means to improve perf ormance, unless they manage to encompass the entire dataset of the

problem.

The Intel I7-920 processor has some 8 MB of internal L3 cache. This cache memory is not free, and

if we look at the die for the Intel I7 processor, we see around 30% of the size of the chip is dedicated to

the L3 cache memory (Figure 1.2).

As cache sizes grow, so does the physical size of the silicon used to make the processors. The

larger the chip, the more expensive it is to manufacture and the higher the likelihood that it will

contain an error and be discarded during the manufacturing process. Sometimes these faul ty devices

are sold cheaply as either triple- or dual-core devices, with the faulty cores disabled. However,

the effect of larger, progress ively more inefﬁcient caches ultimately results in higher costs to the

end user.

Core 1

Shared L3 Cache

Core 2 Core 4Core 3

FIGURE 1.2

Layout of I7 Nehalem processor on processor die.

4 CHAPTER 1 A Short History of Supercomputing

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