AIC3204音频芯片手册：功能与应用详解

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AIC3204Reference Manual是一份详细的音频芯片应用参考指南，主要针对TLV320AIC3204音频编解码器。这款芯片以其灵活性、低功耗和低电压特性而著称，适用于多种音频应用，包括但不限于： 1. **功能亮点**: - 具备6个模拟输入通道，可以是单端或全差分模式，支持可编程输入和输出，以及PowerTune输入能力。 - 内置立体声模拟和数字麦克风输入，信号处理模块具备预定义和可配置选项，适应多样化的录音需求。 - 提供立体声耳机输出和线性输出，确保高保真音频体验。 2. **主要应用场景**: - **便携式导航设备（PND）**: 通过100dB的SNR提供清晰的音频播放，支持4.1声道立体声48kHz采样率输出。 - **便携式媒体播放器（PMP）**: 适合高质量音乐播放，音频ADC具备93dB的信噪比，可进行6.1声道立体声48kHz采样率录音。 - **移动电话**：在手机中实现高级音频处理和通话质量优化。 - **通信设备**: 支持高效的音频通信，如语音编码和解码。 - **移动计算设备**: 在笔记本电脑、平板等设备上提供低功耗的音频处理能力。 - **信号处理选项**：丰富的信号处理功能，可根据具体应用进行定制。 3. **使用流程**: - **设备概述** (Chapter 1): 对TLV320AIC3204的基本架构和功能有全面介绍。 - **应用指南** (Chapter 2): 提供实际应用中的详细步骤和建议，帮助用户了解如何有效地集成和配置该芯片。 - **初始化** (Chapter 3): 包括硬件和软件的初始化设置，确保芯片正常运行。 - **示例搭建** (Chapter 4): 提供典型系统设计的示例，以便快速上手。 - **寄存器映射与描述** (Chapter 5): 描述芯片内部寄存器的功能和操作方法，这对于驱动和控制芯片至关重要。 TLV320AIC3204Reference Manual是一份详尽的文档，为开发者提供了丰富的技术细节和实际应用案例，无论是对于音频硬件设计者还是系统集成工程师来说，都是理解和开发这款音频编解码器的重要参考资料。

RIGHT

DAC AFIR

Output +

LOR

RIGHT_DACP

RIGHT_DACM

LOL

Output -

LOL

LOR

ADC

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Figure 2-8. Stereo Single-Ended Line-out

Figure 2-9. Low Power Mono DAC to Differential Line-out

2.3 ADC

The TLV320AIC3204 includes a stereo audio ADC, which uses a delta-sigma modulator with a

programmable oversampling ratio, followed by a digital decimation filter. The ADC supports sampling rates

from 8kHz to 192kHz. In order to provide optimal system power management, the stereo recording path

can be powered up one channel at a time, to support the case where only mono record capability is

required.

The ADC path of the TLV320AIC3204 features a large set of options for signal conditioning as well as

signal routing:

• Two ADCs

• Six analog inputs which can be mixed and-or multiplexed in single-ended and-or differential

configuration

• Two programmable gain amplifiers (PGA) with a range of 0 to +47.5dB

• Two mixer amplifiers for analog bypass

• Two low power analog bypass channels

• Fine gain adjustment of digital channels with 0.1dB step size

• Digital volume control with a range of -12 to +20dB

• Mute function

• Automatic gain control (AGC)

In addition to the standard set of ADC features the TLV320AIC3204 also offers the following special

functions:

TLV320AIC3204 Application SLAA557–November 2012

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Analog

Gain

Analog

Input

Selection

ADC

Filtering

Digital

Volume

Control

Digital

Gain

Adjust

0...47.5 dB

Step = 0.5 dB

0, -6, -12 dB -12...20 dB

Step = 0.5 dB

0…-0.4 dB

Step= 0.1 dB

Frequency

Response

and Gain

Fully

Programmable

Coefficients

Audio

Interface

ADC

PGA

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ADC

• Built in microphone bias

• Stereo digital microphone interface

• Channel-to-channel phase adjustment

• Fast charge of ac-coupling capacitors

• Anti thump

• Adaptive filter mode

Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,

requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC3204 integrates a second

order analog anti-aliasing filter with 28-dB attenuation at 6MHz. This filter, combined with the digital

decimation filter, provides sufficient anti-aliasing filtering without requiring additional external components.

2.3.1 ADC Signal Routing

As shown in Figure 2-1, the TLV320AIC3204 includes six analog inputs which can be configured as either

3 stereo single-ended pairs or 3 fully-differential pairs. These pins connect through series resistors and

switches to the virtual ground terminals of two fully-differential amplifiers (one per ADC-PGA channel). By

turning on only one set of switches per amplifier at a time, the inputs can be effectively multiplexed to

each ADC PGA channel. By turning on multiple sets of switches per amplifier at a time, audio sources can

be mixed. The TLV320AIC3204 supports the ability to mix up to four single-ended analog inputs or up to

two fully-differential analog inputs into each ADC PGA channel.

In most applications, high input impedance is desired for analog inputs. However, when used in

conjunction with high gain as in the case of microphone inputs, the higher input impedance results in

higher noise or lower dynamic range. The TLV320AIC3204 allows the user the flexibility of choosing the

input impedance from 10kΩ, 20kΩ and 40kΩ. When multiple inputs are mixed together, by choosing

different input impedances, level adjustment can be achieved. For example, if one input is selected with

10kΩ input impedance and the second input is selected with 20kΩ input impedance, then the second input

is attenuated by half as compared to the first input. Note that this input level control is not intended to be a

volume control, but instead used occasionally for level setting.

Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal amplifiers,

resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented, the

system designer is advised to take adequate precautions to avoid such a saturation from occurring. In

general, the mixed signal should not exceed 0dB.

Typically, voice or audio signal inputs are capacitively coupled to the device. Capacitive coupling allows

the device to independently set the common mode of the input signals to values chosen by the contents of

Page 1, Register 10, D(6) to either 0.9V or 0.75V. The correct value maximizes the dynamic range across

the entire analog-supply range. Failure to capacitively connect the input to the device can cause high

offset due to mismatch in source common-mode and device common-mode setting, and in extreme cases,

could also saturate the analog channel, causing distortion.

2.3.2 ADC Gain Setting

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When the gain of the ADC Channel is kept at 0dB and the common mode set to 0.75V, a single-ended

input of 0.375V

RMS

results in a full-scale digital signal at the output of ADC channel. Similarly, when the

gain is kept at 0dB, and common mode is set to 0.9V, a single-ended input of 0.5V

RMS

results in a full-

scale digital signal at the output of the ADC channel. However various block functions control the gain

through the channel. The gain applied by the PGA is described in Table 2-4. Additionally, the digital

volume control adjusts the gain through the channel as described in Section 2.3.2.2. A finer level of gain is

controlled by fine gain control as described in Section 2.3.2.2.1. The decimation filters A, B and C along

with the delta-sigma modulator contribute to a DC gain of 1.0 through the channel.

2.3.2.1 Analog Programmable Gain Amplifier (PGA)

The TLV320AIC3204 features a built-in low-noise PGA for boosting low-level signals, such as direct

microphone inputs, to full-scale to achieve high SNR. This PGA provides a gain in the range of 0dB to

47.5dB for single-ended inputs or 6dB to 53.5dB for fully-differential inputs (gain calculated w.r.t. input

impedance setting of 10kΩ, 20kΩ input impedance will result in 6dB lower and 40kΩ will result in 12dB

lower gain). The user can control the gain by writing to Page 1, Register 59 and Page 1, Register 60. In

the AGC mode, this gain is optionally automatically controlled by the built-in hardware AGC.

Table 2-4. Analog PGA versus Input Configuration

Page 1, EFFECTIVE GAIN APPLIED BY PGA

SINGLE-ENDED DIFFERENTIAL

Page 1,

= 10kΩ R

= 20kΩ R

= 40kΩ R

= 10kΩ R

= 20kΩ R

= 40kΩ

000 0000 0dB –6dB -12dB 6.0dB 0dB –6.0dB

000 0001 0.5dB –5.5dB –11.5dB 6.5dB 0.5dB -5.5dB

000 0010 1.0dB –5.0dB –11.0dB 7.0dB 7.5dB –5.0dB

… … … … … … …

101 1110 47.0dB 41.0dB 35.0dB 53.0dB 47.0dB 41.0dB

101 1111 47.5dB 41.5dB 35.5dB 53.5dB 47.5dB 41.5dB

The gain changes are implemented with an internal soft-stepping algorithm that only changes the actual

volume level by one 0.5dB step every one or two ADC output samples, depending on the register value

(see registers Page 0, Reg 81, D(1:0)). This soft-stepping smooths volume control changes with no

audible artifacts. On reset, the PGA gain defaults to a mute condition, and at power down, the PGA soft-

steps the volume to mute before shutting down. A read-only flag Page 0, Reg 36, D(7) and D(3) is set

whenever the gain applied by the PGA equals the desired value set by the register. The soft-stepping

control can also be disabled by programming Page 0, Reg 81, D(1:0).

2.3.2.2 Digital Volume Control

The TLV320AIC3204 also has a digital volume-control block with a range from -12dB to +20dB in steps of

0.5dB. The system controls the volume by programming Page 0, Register 83 and 84 respectively for left

and right channels.

Table 2-5. Digital Volume Control for ADC

Desired Gain Left or Right Channel

dB Page 1, Register 83 or 84 (respectively),

D(6:0)

–12.0 110 1000

–11.5 110 1001

–11.0 110 1010

–0.5 111 1111

0.0 000 0000 (Default)

+0.5 000 0001

TLV320AIC3204 Application SLAA557–November 2012

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ADC

Table 2-5. Digital Volume Control for ADC (continued)

Desired Gain Left or Right Channel

dB Page 1, Register 83 or 84 (respectively),

D(6:0)

+19.5 010 0111

+20.0 010 1000

During volume control changes, using the soft-stepping feature avoids audible artifacts. The soft-stepping

rate can be set to either 1 or 2 gain steps per sample. Soft-stepping can also be entirely disabled. This

soft-stepping is configured via Page 1, Register 81, D(1:0), and is common to the soft-stepping control for

the analog PGA. During power-down of an ADC channel, this volume control soft-steps down to –12.0dB

before powering down. Due to the soft-stepping control, soon after changing the volume control setting or

powering down the ADC channel, the actual applied gain may be different from the one programmed

through the control register. The TLV320AIC3204 gives feedback to the user, through read-only flags

Page 1, Reg 36, D(7) for Left Channel and Page 1, Reg 36, D(3) for the right channel.

2.3.2.2.1 Fine Digital Gain Adjustment

Additionally, the gain in each of the channels is finely adjustable in steps of 0.1dB. This granularity is

useful when trying to match the gain between channels. By programming Page 0, Register 82 the gain

can be adjusted from 0dB to -0.4dB in steps of 0.1dB. This feature, in combination with the regular digital

volume control, allows the gains through the left and right channels be matched in the range of -0.5dB to

+0.5dB with a resolution of 0.1dB.

2.3.2.3 AGC

The TLV320AIC3204 includes Automatic Gain Control (AGC) for ADC recording. AGC can be used to

maintain a nominally-constant output level when recording speech. As opposed to manually setting the

PGA gain, in the AGC mode, the circuitry automatically adjusts the PGA gain as the input signal becomes

overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from

the microphone. The AGC algorithm has several programmable parameters, including target gain, attack

and decay time constants, noise threshold, and max PGA applicable, that allow the algorithm to be fine

tuned for any particular application. The algorithm uses the absolute average of the signal (which is the

average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal.

Since the gain can be changed at the sample interval time, the AGC algorithm operates at the ADC

sample rate.

1. Target Level represents the nominal output level at which the AGC attempts to hold the ADC output

signal level. The TLV320AIC3204 allows programming of eight different target levels, which can be

programmed from –5.5dB to –24dB relative to a full-scale signal. Since the TLV320AIC3204 reacts to

the signal absolute average and not to peak levels, it is recommended that the target level be set with

enough margin to avoid clipping at the occurrence of loud sounds.

2. Attack Time defines how quickly the AGC circuitry reduces the PGA gain when the output signal level

exceeds the target level due to increase in input signal level. Wide range of attack time

programmability is supported in terms of number of samples (number of ADC sample frequency clock

cycles).

3. Decay Time defines how quickly the PGA gain is increased when the output signal level falls below

the target level due to reduction in input signal level. Wide range of decay time programmability is

supported in terms of number of samples.

4. Gain Hysteresis is the hysteresis applied to the required gain calculated by the AGC function while

changing its mode of operation from attack to decay or vice-versa. For example, while attacking the

input signal, if the current applied gain by the AGC is xdB, and suddenly because of the input level

going down, the new calculated required gain is ydB, then this gain is applied, provided that y is

greater than x by the value set in Gain Hysteresis. This feature avoids the condition where the AGC

function fluctuates between a very narrow band of gains leading to audible artifacts. The Gain

Hysteresis can be adjusted or disabled by the user.

5. Noise threshold defines the level below which if the input signal level falls, the AGC considers it as

silence, and thus brings down the gain to 0dB in steps of 0.5dB every f

and sets the noise threshold

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zD2

zNN

)z(H

ADC

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flag. The gain stays at 0dB unless the input speech signal average rises above the noise threshold

setting. This noise-gating ensures that noise is not 'gained up' in the absence of speech. Noise

threshold level in the AGC algorithm is programmable from -30dB to -90dB of full-scale. When AGC

Noise Threshold is set to –70dB, –80dB, or –90dB, the microphone input Max PGA applicable setting

must be greater than or equal to 11.5dB, 21.5dB, or 31.5dB respectively. This operation includes

hysteresis and debounce to avoid the AGC gain from cycling between high gain and 0dB when signals

are near the noise threshold level. The noise (or silence) detection feature can be entirely disabled by

the user.

6. Max PGA applicable allows the designer to restrict the maximum gain applied by the AGC. This

feature limits PGA gain in situations where environmental noise is greater than the programmed noise

threshold. Microphone input Max PGA is programmable from 0dB to 58dB in steps of 0.5dB.

7. Hysteresis, as the name suggests, defines a window around the Noise Threshold which must be

exceeded to either detect that the recorded signal is indeed noise or signal. If initially the energy of the

recorded signal is greater than the Noise Threshold, then the AGC recognizes it as noise only when

the energy of the recorded signal falls below the Noise Threshold by a value given by Hysteresis.

Similarly, after the recorded signal is recognized as noise, for the AGC to recognize it as a signal, its

energy must exceed the Noise Threshold by a value given by the Hysteresis setting. In order to

prevent the AGC from jumping between noise and signal states, (which can happen when the energy

of recorded signal is very close to the Noise threshold) a non-zero hysteresis value should be chosen.

The Hysteresis feature can also be disabled.

8. Debounce Time (Noise and Signal) defines the hysteresis in time domain for noise detection. The

AGC continuously calculates the energy of the recorded signal. If the calculated energy is less than the

set Noise Threshold, then the AGC does not increase the input gain to achieve the Target Level.

However, to handle audible artifacts which can occur when the energy of the input signal is very close

to the Noise Threshold, the AGC checks if the energy of the recorded signal is less than the Noise

Threshold for a time greater than the Noise Debounce Time. Similarly the AGC starts increasing the

input-signal gain to reach the Target Level when the calculated energy of the input signal is greater

than the Noise Threshold. Again, to avoid audible artifacts when the input-signal energy is very close

to Noise Threshold, the energy of the input signal needs to continuously exceed the Noise Threshold

value for the Signal Debounce Time. If the debounce times are kept very small, then audible artifacts

can result by rapid enabling and disabling the AGC function. At the same time, if the Debounce time is

kept too large, then the AGC may take time to respond to changes in levels of input signals with

respect to Noise Threshold. Both noise and signal debounce time can be disabled.

9. The AGC Noise Threshold Flag is a read-only flag indicating that the input signal has levels lower

than the Noise Threshold, and thus is detected as noise (or silence). In such a condition the AGC

applies a gain of 0dB.

10. Gain Applied by AGC is the gain applied by the AGC to the recorded signal in a read-only register to

provide real-time feedback to the system. This value, along with the Target Setting, can be used to

detect the input signal level. In a steady state situation

Target Level (dB ) = Gain Applied by AGC (dB) + Input Signal Level (dB)

When the AGC noise threshold flag is set, then the status of gain applied by AGC should be ignored.

11. The AGC Saturation Flag is a read-only flag indicating that the ADC output signal has not reached its

Target Level. However, the AGC is unable to increase the gain further because the required gain is

higher than the Maximum Allowed PGA gain. Such a situation can happen when the input signal has

very low energy and the Noise Threshold is also set very low. When the AGC noise threshold flag is

set, the status of the AGC saturation flag should be ignored.

12. The ADC Saturation Flag is a read-only flag indicating an overflow condition in the ADC channel. On

overflow, the signal is clipped and distortion results. This condition typically happens when the AGC

Target Level is kept very high and the energy in the input signal increases faster than the Attack Time.

13. An AGC low-pass filter detects the average level of the input signal. This average level is compared

to the programmed detection levels in the AGC to provide the correct functionality. This low pass filter

is in the form of a first-order IIR filter. Three 8-bit registers form the 24-bit digital coefficient as shown

on the register map. A total of 9 registers are programmed to form the 3 IIR coefficients. The transfer

function of the filter implemented for signal level detection is given by

(2)

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