边界扫描测试理论与应用

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"这篇教程介绍了边界扫描测试理论，也称为BScan测试，是电子硬件测试领域的一种重要技术，尤其在电路板级测试中广泛应用。该技术由IEEE1149.1标准定义，旨在简化集成电路(IC)的测试，提高生产效率，并能检测封装后的电路故障。" 边界扫描测试(Boundary-Scan)是一种集成电路测试方法，它允许在电路组装后进行内部连接的测试，而无需复杂的物理探针接触。这种方法特别适用于那些因为封装或密度高而难以用传统测试手段检查的芯片。 1. **边界扫描架构的动机** (Chapter 1: The Motivation for Boundary-Scan Architecture) 边界扫描设计的初衷是为了克服传统的在电路板上进行的在线电路测试（In-Circuit Test, ICT）的局限性。ICT往往需要物理接触每个组件，这在高密度封装和多层电路板中变得困难且成本高昂。边界扫描提供了一种替代方案，通过在IC内部集成特殊测试结构来验证内部连接的完整性。 2. **边界扫描原理** (Chapter 2: The Principle of Boundary-Scan Architecture) 使用扫描路径(Scan Path)是边界扫描的核心概念。每个边界扫描细胞(Boundary-Scan Cell)位于IC输入/输出(I/O)端口处，能够存储和传递数据。这些细胞形成一个环形链路，允许测试数据沿链路移动，从而在不改变正常信号路由的情况下检查内部连接。 3. **IEEE 1149.1设备架构** (Chapter 3: IEEE 1149.1 Device Architecture) - **指令寄存器**(Instruction Register)：控制边界扫描操作的命令中心，通过设置不同的指令执行各种测试模式。 - **指令**(Instructions)：包括多种预定义的测试操作，如数据捕获、数据传输、测试逻辑重置等。 - **使用指令寄存器(IR)**：通过TAP访问并编程IR，以指定所需的测试序列。 - **“Capture-01”模式**：用于捕获输入/输出端口的状态。 - **测试访问端口(TAP)**：控制边界扫描功能的硬件接口。 - **旁路寄存器**(Bypass Register)：允许数据直接通过扫描链，不执行任何测试操作。 - **标识寄存器**(Identification Register)：存储设备的识别信息。 - **lsb=1特性**：用于特定测试模式下的数据处理。 - **边界扫描寄存器**(Boundary-Scan Register)：存储每个I/O端口状态的专用存储区。 4. **在电路板级的应用** (Chapter 4: Application at the Board Level) - **一般策略**：利用边界扫描技术进行整体的系统测试和故障隔离。 - **互联测试示例**：演示如何检测和诊断板级连接问题。 - **使用边界扫描技术的实用方面**：涵盖了实际应用中的挑战，如测试覆盖率、测试时间优化以及与软件测试的整合。边界扫描测试理论是现代电子制造中不可或缺的一部分，它提高了生产过程的可靠性，减少了制造成本，并确保了产品在出厂前的高质量。通过理解并有效应用这些理论，工程师可以更有效地诊断和修复电路板上的问题，从而提升产品的质量和客户满意度。

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Boundary-Scan Tutorial

Chapter 3: IEEE 1149.1 Device Architecture

After nearly five years of discussion, the JTAG organization finally proposed the architecture shown in Figure 8.

Test Data In

TDI

Test Data Out

TDO

Test Mode Select

TMS

Test Clock

TCK

Bypass register

Test Reset

TRST* (optional)

Any Digital Chip

Any Internal Register

Identification Register

Boundary-Scan Register

Instruction Register

TAP

Controller

Figure 8: IEEE 1149.1 Chip Architecture

Figure 8 shows the following elements:



A set of four dedicated test pins — Test Data In (TDI), Test Mode Select (TMS), Test Clock (TCK), Test Data

Out (TDO) — and one optional test pin Test Reset (TRST*). These pins are collectively referred to as the Test

Access Port (TAP).



A boundary-scan cell on the device primary input and primary output pins of a device, connected internally to

form a serial boundary-scan register (Boundary Scan).



A finite-state machine TAP controller with inputs TCK, TMS, and TRST*.



An n-bit (n ≥ 2) Instruction Register (IR), holding the current instruction.



A 1-bit bypass register (Bypass).



An optional 32-bit Identification Register (Ident) capable of being loaded with a permanent device identification

code.

At any time, only one register can be connected from TDI to TDO (e.g., IR, Bypass, Boundary-scan, Ident, or even

some appropriate register internal to the core logic). The selected register is identified by the decoded output of the

IR. Certain instructions are mandatory, such as Extest (boundary-scan register selected), whereas others are

optional, such as the Idcode instruction (Ident register selected).

Let’s take a closer look at each part of this architecture.

The Instruction Register

An Instruction Register (IR) has a shift section that can be connected to TDI and TDO, and a hold section, holding

the current instruction as shown in Figure 9.

Boundary-Scan Tutorial

Figure 9: The Instruction Register

There may be some decoding logic between the two sections depending on the width of the register and the

number of different instructions. The control signals to the IR originate from the TAP controller and either cause a

shift-in, shift-out through the IR shift section, or cause the contents of the shift section to be passed across to the

hold section (update operation). It is also possible to load (capture) certain hard-wired values into the shift section

of the IR. The IR must be at least two-bits long (to allow coding of the four mandatory instructions — Bypass,

Sample, Preload, Extest — but the maximum length of the IR is not defined. In capture mode, the two least

significant bits must capture a 01 pattern (see Figure 9). The values captured into higher-order bits are not defined.

One possible use of these higher order bits is to capture an informal identification code if the 32-bit Ident register is

not implemented. In practice, the only mandated bit pattern for IR capture is the 01 pattern. We will return to the

value of capturing this pattern later in this tutorial.

The Instructions

The IEEE 1149.1-2001 version of the Standard describes four mandatory instructions: Bypass, Sample, Preload,

and Extest.

The Bypass instruction must be assigned an all-1s code. When executed, the Bypass instruction causes the

Bypass register to be placed between the TDI and TDO pins. By definition, the initialized state of the hold section of

the IR should contain the Bypass instruction code unless the optional Identification Register (Ident) has been

implemented, in which case, the Idcode instruction code should be present in the hold section.

The Sample and Preload instructions both select the boundary-scan register when executed. The Sample

instruction sets up the boundary-scan cells to sample (capture) values moving into the device. The Preload

instruction is used to preload known values into the output boundary-scan cells prior to some follow-on operation.

The codes for the Sample and Preload instructions are not defined.

The Extest instruction selects the boundary-scan register preparatory to interconnect testing. Prior to the 2001

version of the Standard, the code for Extest was defined to be the all-0s code. Since 2001, the code is no longer

defined.

The IEEE 1149.1 Standard defines a number of optional instructions (instructions that do not need to be

implemented, but which have a prescribed operation when they are used). Examples of optional instructions

include:

Intest, the instruction that selects the boundary-scan register preparatory to applying tests to the core logic of the

device.

Idcode, the instruction that selects the Identification Register between TDI and TDO preparatory to loading the

internal hard-wired Idcode values and reading them out through TDO. Note that if the Idcode instruction is loaded

and there is no Identification Register present on the device, then the Idcode instruction must be interpreted as if it

were the Bypass instruction.

Boundary-Scan Tutorial

The Runbist instruction initiates an internal self-test routine and places the pass/fail result register between TDI and

TDO.

Two new instructions were introduced in the 1993 revision, 1149.1a. These were Clamp and Highz. Clamp is an

instruction that drives preset scan-cell values onto the outputs of devices (established initially with the Preload

instruction) and then selects the Bypass register between TDI and TDO. Clamp would be used to set up safe

“guarding” values on the outputs of certain devices in order to avoid bus contention problems, for example.

Highz is similar to Clamp, but the device is designed such that all outputs can be placed in either a high-Z mode (3-

state outputs) or input receive mode (for bidirectional scan cells). HighZ establishes these values on the output pins

but leaves the Bypass register as the selected register Note that the Enable control signal to do this is supplied

directly from the IR upon execution of the HighZ instruction. Preload is not used.

With the exception of Bypass, the codes for all instructions are undefined. Given the need for four mandatory

instructions, the minimum length of the IR is two bits. The maximum length is undefined. Any instruction can have

more than one code and all unused codes are interpreted as Bypass. Note that the designer may use certain codes

to implement “private” instructions — that is, instructions whose functions are not made public. In these

circumstances, the designer must state that these codes are private so that the user can avoid loading the codes.

Using the Instruction Register (IR)

Before proceeding with a description of other parts of the architecture, we will first examine how to load the IR and

decode its contents. Consider the board circuit shown in Figure 10.

Figure 10: Using the Instruction Register — Step 1

Assume that what we want to do is to place Chip 1 into bypass mode (to shorten the time it takes to get test

stimulus to devices farther down the scan chain) and place chips 2 and 3 into Extest mode preparatory to setting up

tests to check the interconnect between Chips 2 and 3. This set-up requires loading the Bypass instruction (all-1s)

into the IR of chip 1 and the Extest instruction (assumed to be all-0s for Chips 2 and 3) into the IRs of Chips 2 and

Step 1 connects the IRs of all three devices between their respective TDI and TDO pins. This is achieved by a

special sequence of values on the serial control line TMS going to each TAP controller. Note that the TMS (and

TCK) lines are connected to all devices in parallel. Any sequence of values on TMS will be interpreted in the same

way by each TAP controller. Later, we will see the precise TMS sequence to select the IR between TDI and TDO.

For now, we will assume that such a sequence exists.

Step 2 loads the appropriate instructions into the various IRs via the global connection of IRs. If we assume simple

two-bit IRs per device, this operation amounts to a serial load of the sequence 110000 into the edge-connector TDI

to place 00 in the IRs of Chips 2 and 3, and 11 in the IR of Chip 1. The IRs are now set up with the correct

instructions loaded into their shift sections.

Step 3, shown in Figure 11, places further values on TMS to cause each TAP controller to issue the control-signal

values to transfer the values in the shift sections of the IRs to the hold sections where they become the current

Boundary-Scan Tutorial

instruction. This is the Update operation. At this point, the various instructions are obeyed — that is, Chip 1

deselects the IR and selects the Bypass register between TDI and TDO (Bypass instruction), and Chips 2 and 3

deselect their IRs and select their boundary-scan registers between TDI and TDO (Extest instruction). The devices

are now set up and ready for the Extest operation.

 Step 2: decode and execute new instructions. New target

registers are selected

 Devices now set up to apply interconnect tests between

devices 2 and 3

TDI

TMS

TCK

TDO

1 2 3

Figure 11: Using the Instruction Register — Step 3

Use of the “Capture 01” Mode

Previously we discussed the capture of the fixed 01 pattern into the least two significant positions of the Instruction

the use of the “capture 01” pattern?

To answer this question, we need to think about the use of boundary-scan architecture at the board level. Consider

again the circuit in Figure 10.

Previously, we saw how to set up a test environment preparatory to carrying out interconnect tests. To do this, we

made use of the test infrastructure (i.e., the on-chip boundary-scan features plus the board-level TMS and TCK

connections and the chip-to-chip TDO-to-TDI interconnects). It is important to know that this infrastructure is fault-

free before making use of it. In other words, we must first “test the tester” before using the tester to test other parts

of the board. This is the purpose of the IR capture 01 operation.

Essentially, the following happens:

Step 1: Apply the sequence to TMS, which causes each device to place the IR between TDI and TDO. At this

stage, there is a serial shift register that starts at the board TDI input and ends at the board TDO output

and which is made up of the various IRs in the devices — an IR chain.

Step 2: Apply an additional sequence to TMS to cause each IR to capture the hardwired 01 into the least two

significant positions of the IR shift register. Higher-order bits capture what they are set up to capture.

These values are not mandated by the Standard. The captured 01 values constitute a checkerboard

“flush” test for the serial IR chain.

Step 3: Clock the captured values out of the IR chain to the board’s TDO output while clocking in he instruction

code sequence 110000.

If the sequence TDO: 10…10…10… emerges, then we can be reasonably sure of the following facts:



The TMS control signal is properly connected from the board’s TMS input to the TMS inputs of every device.



The TCK control signal is properly connected from the board’s TCK input to the TCK inputs of every device.



The TDO from one device is properly connected to the TDI of its logical neighbor.



Each internal TAP controller is at least capable of responding correctly to the sequences on TMS that cause

the IR both to capture and to shift.

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