入门指南：时序约束源同步接口详解与分析

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"时序约束资料"是一份由Altera Corporation在2016年发布的应用笔记，名为"AN433: Constraining and Analyzing Source-Synchronous Interfaces"。这份文档专为初学者设计，详细介绍了如何处理和分析源同步接口的时序问题。源同步接口是一种高速数据传输模式，其中数据源和时钟源来自同一设备，如DDR内存、HyperTransport总线和SPI-4.2标准都采用这种架构。在源同步接口中，确保正确的时序至关重要，因为它们涉及到数据和时钟之间的精确同步。这不仅影响到系统的性能，还可能决定其能否达到预期的工作速度和稳定性。文档强调了时序分析的复杂性，并指出Synopsys Design Constraints (SDC) 格式在进行有效分析时必不可少。SDC提供了一种精确描述设计约束的工具，这对于理解和优化时序行为是至关重要的。在阅读这份应用笔记之前，建议读者首先熟悉SDC格式以及Quartus II的TimeQuest Timing Analyzer。TimeQuest Timing Analyzer是一款用于设计验证和时序分析的工具，它能够帮助工程师分析时序路径、确定延迟、设置时序约束等，从而确保设计满足系统时序要求。此外，应用笔记中还可能包含以下内容： 1. 接口概述：介绍源同步接口的基本结构和工作原理，包括数据和时钟的同步机制。 2. 时序约束类型：讲解不同的时序约束，如setup时间、hold时间、setup-hold时间等，以及它们在设计中的作用。 3. 常见问题与挑战：列出在设计过程中可能遇到的挑战，如信号完整性、噪声敏感性等，以及如何通过合理的约束来解决这些问题。 4. 案例研究：通过具体的例子展示如何在实际项目中应用SDC和TimeQuest Timing Analyzer进行约束和分析。 5. 最佳实践：分享优化源同步接口时序约束的实用技巧和策略，以提升设计效率和性能。 6. 参考文献：提供进一步学习和深入理解的资源，如官方手册、API文档等。这份应用笔记是设计者和初学者理解并管理源同步接口时序约束的重要参考资料，它将理论知识与实践经验相结合，为高效的设计和分析提供了全面的指导。

Page 10 Source-Synchronous Outputs

AN 433: Constraining and Analyzing Source-Synchronous Interfaces © May 2016 Altera Corporation

Figure 15 and Example 7 show the circuit and constraints for one PLL output driving

the data DDR registers, and a separate PLL output driving the clock DDR registers.

Figure 16 and Example 8 show the circuit and constraints for a PLL that drives the

clock directly off chip.

Example 6. Clock Constraints for an Edge-Aligned Output with Common Data and Output Clocks

create_clock -name input_clock -period 10.000 [get_ports clk_in]

create_generated_clock -name common_clock -source \

[get_pins PLL|inclk[0]] [get_pins PLL|clk[0]]

create_generated_clock -name output_clock -source \

[get_pins DDR|ddio_outa[0]|muxsel] [get_ports clk_out]

Figure 15. Output Circuit with Separate Output Clock and Input Clocks

FPGA

PLL

datain_h

datain_i

outclock

data_out

clock_out

DDR

clk_in

Example 7. Clock Constraints for an Output with Independent Data and Output Clocks

create_clock -name input_clock -period 10.000 [get_ports clk_in]

create_generated_clock -name data_clock -source [get_pins PLL|inclk[0]] \

[get_pins PLL|clk[0]]

create_generated_clock -name pll_clock -source [get_pins PLL|inclk[0]] \

[get_pins PLL|clk[1]]

create_generated_clock -name output_clock -source \

[get_pins DDR|ddio_outa[0]|muxsel] [get_ports clk_out]

Figure 16. Output Circuit, Driving Clock Directly Off Chip

FPGA

PLL

datain_h

datain_i

outclock

data_out

clock_out

DDR

clk_in

Page 12 Source-Synchronous Outputs

AN 433: Constraining and Analyzing Source-Synchronous Interfaces © May 2016 Altera Corporation

Output Minimum Delay

Equation 2 shows how to calculate the output minimum delay value. The output

minimum delay specifies a lower band for the output delay because it uses the

minimum data delay and the maximum clock delay. It defines the hold relationship

with the destination register.

Example 11 shows the output minimum delay SDC constraint, with the output

minimum delay value from Equation 2. This example is useful if your

source-synchronous interface contains an SDR output.

Example 12 shows a DDR output that has a duplicate constraint that applies to the

falling clock edge.

Using the -clock_fall option causes the output delay constraint to apply to the

falling clock edge. Using the -add_delay option allows multiple output delays to

apply to the data_out ports.

System-Centric Output Timing Exceptions

The following sections describe different alignment and capture edge combinations,

and show any additional timing exceptions or adjusted constraints that are

appropriate for each combination. For additional timing exceptions or constraint

modifications that are necessary for the correct operation, refer to one of the following

use cases:

■ “Same-Edge Capture Edge-Aligned Output” on page 13

■ “Opposite-Edge Capture Edge-Aligned Output” on page 16

Example 10. Output Maximum Delay Constraints for a DDR Output

set_output_delay -max <output maximum delay value> -clock \

[get_clocks output_clock] [get_ports data_out]

set_output_delay -max <output maximum delay value> -clock \

[get_clocks output_clock] -clock_fall [get_ports data_out]

-add_delay

Equation 2. Output Minimum Delay Calculation

Example 11. Output Minimum Delay Constraint

set_output_delay -min <output minimum delay value> -clock \

[get_clocks output_clock] [get_ports data_out*]

Example 12. Output Minimum Delay Constraints for a DDR Output

set_output_delay -min <output minimum delay value> -clock \

[get_clocks output_clock] [get_ports data_out*]

set_output_delay -min <output minimum delay value> -clock \

[get_clocks output_clock] -clock_fall [get_ports data_out*] \

-add_delay

output minimum delay minimum trace delay for data t

of external register–

maximum trace delay for clock

–=

剩余55页未读，继续阅读

zcl_33

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