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首页HMS Anybus-S开发设计指南:DP卡集成与系统详解
HMS Anybus-S开发设计指南:DP卡集成与系统详解
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更新于2024-07-21
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本篇文档是HMS Industrial Networks公司发布的"Anybus SSlave&Master"系列模块的开发设计指南,标题为"Parallel Interface Design Guide"。该文档主要针对的是Profibus-DP技术,DP卡作为HMS公司的套件产品,旨在为用户深入理解该模块提供的功能提供详尽的指导。 文档首先强调了读者需具备高级软件设计和一般通信系统知识背景,以便更好地理解和应用。重要用户信息部分指出,尽管作者在准备过程中已尽力确保内容的准确性,但读者需了解手册中的数据和示例可能并非最终版,HMS Industrial Networks AB保留根据持续的产品开发策略对产品进行修改的权利。这意味着信息可能会随时间变化,不应视为对HMS工业网络承诺的正式约束。 在文档的核心部分,读者可以期待学习到关于Anybus SSlave和Master模块的接口设计细节,包括但不限于模块的工作原理、协议实现、硬件配置、数据传输特性以及如何与不同的DP设备进行有效连接。此外,可能涉及的内容还包括错误处理、通信性能优化、以及与不同操作系统和编程语言的集成方法。为了充分利用这些功能,开发者需要遵循文档中的指导,以确保系统的可靠性和兼容性。 这是一份技术密集型的参考资料,涵盖了从理论到实践的关键知识点,对于想要在Profibus-DP环境下进行系统设计、编程或维护的工程师来说,是不可或缺的工具。通过阅读并遵循这份文档,用户将能更好地利用Anybus S系列模块,提升其工业自动化解决方案的效率和可靠性。
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Application Connector 14
Doc.Id. HMSI-27-275
Anybus-S Slave & Master
Doc.Rev. 3.00
Data Input / Output (D
0
... D
7
)
Data output pins during read operations, or data input pins during write operations. D
0
is the least sig-
nificant bit, D
7
is the most significant.
The target memory location is specified on the Address Inputs (A
0
... A
11
).
Busy Signal (BUSY)
Active low open collector output, internally pulled up with 10k.When low, this pin indicates that the
desired address is currently in use by the Anybus module, and can be used to insert wait states to stall
the current operation until the module is ready.
Interrupt Request (IRQ)
Active low open collector output, internally pulled up with 10k. When low, this pin indicates that new
information is available in the Anybus Indication Register (7FFh). It is strongly recommended to imple-
ment this signal on the host application.
Output Enable (OE)
Enables data output on D
0
... D
7
when low.
Read/Write (R/W)
Enables data input on D
0
... D
7
when low. Internally pulled up with 10k.
Chip Enable (CE)
Active low input (though pulled up on most modules); enables communication with the application in-
terface. CE
must only be active during access of the DPRAM. Internally pulled up with 10k unless
otherwise stated in section ‘Application Interface Hardware Deviances’.
Reset (RESET)
If low, a system reset is initiated.
Internally pulled up with 10k - 75k and decoupled to ground with a 10 - 100nF capacitor.
Application Connector 15
Doc.Id. HMSI-27-275
Anybus-S Slave & Master
Doc.Rev. 3.00
2.3 Asynchronous Serial Interface
These pins are generally used for firmware upgrades etc., see “Firmware Upgrade” on page 65.
For signal characteristics etc., see “Signal Characteristics” on page 79.
Transmit Data (TxD)
Asynchronous serial data transmit signal. Internally pulled up with 10k. Anybus modules with 3,3 to
5V conversion of the Tx signal does not have the 10k resistor. The signal is driven high or low by the
buffer circuit instead. See also “Application Interface Hardware Deviances” on page 75.
Receive Data (RxD)
Asynchronous serial data receive signal. Internally pulled up with 10k.
Doc.Id. HMSI-27-275
Anybus-S Slave & Master
Doc.Rev. 3.00
Chapter 3
3. Memory Map
The dual port memory is subdivided into several smaller areas based on their usage, see memory map
below.
Note: Implementing A11 in the application will affect the memory map. See “Extended Memory Mode
(4K DPRAM)” on page 73 for further information.
Address: Area: Access: Notes:
000h - 1FFh
Input Data Area R/W See “Fieldbus Data Exchange” on page 36
200h - 3FFh Output Data Area RO See “Fieldbus Data Exchange” on page 36
400h - 51Fh Mailbox Input Area R/W See “Mailbox Interface” on page 39
520h - 63Fh Mailbox Output Area RO See “Mailbox Interface” on page 39
640h - 7BFh
Fieldbus Specific Area - (Consult separate fieldbus appendix)
7C0h - 7FDh
Control Register Area R/W See “Control Register Area” on page 17
7FEh - 7FFh
Handshake Registers
R/W
See “Handshaking & Indication Registers” on
page 25
These areas must be allocated before access. See “Handshaking & Indication Registers” on
page 25.
These areas can be accessed directly.
Doc.Id. HMSI-27-275
Anybus-S Slave & Master
Doc.Rev. 3.00
Chapter 4
4. Control Register Area
This area contains information about the Anybus module; revision, initialization parameters, fieldbus
type and status etc. This area also contains registers for Watchdog handling and Event Notification han-
dling.
Note: Generally, the Control Register Area must be allocated by the application before access. Howev-
er, during module initialization, it is allowed to read static data such as software revision, fieldbus type,
module type etc. without handshaking.
Address: Register: Access: Notes:
7C0h - 7C1h Bootloader Version RO
7C2h - 7C3h
Application Interface Software Version
a
a. On modules with application interface versions prior to 2.00, this register is reserved and should be zero.
RO
7C4h - 7C5h
Fieldbus software version
a
RO
7C6h - 7C9h Module Serial Number RO Unique serial number
7CAh - 7CBh Vendor ID RO Manufacturer ID number (HMS, other)
7CCh - 7CDh Fieldbus Type RO Fieldbus type identifier
7CEh - 7CFh Module Software Version RO Software revision
7D0h - 7D1h
(reserved) -
7D2h - 7D3h Watchdog Counter Input R/W Application controlled Watchdog counter
7D4h - 7D5h Watchdog Counter Output RO Counter, incremented each 1ms
7D6h - 7D9h
(reserved) -
7DAh - 7DDh LED Status RO Current status of each fieldbus status indicator
7DEh - 7DFh
(reserved) -
7E0h - 7E1h Module Type RO Module type, master, slave, other.
7E2h - 7E3h Module Status RO Bit information; freeze, clear etc.
7E4h - 7EBh Changed Data Field RO Bit field, indicating changes in the Output Data
Area in the Dual Port Memory
7ECh - 7EDh Event Notification Cause R/W Event cause register
7EEh - 7EFh Event Notification Source RO Configuration register for Event Notification
7F0h - 7F1h Input I/O Length RO Input I/O size
7F2h - 7F3h Input DPRAM Length RO Number of input I/O bytes in dual port memory
7F4h - 7F5h Input Total Length RO Total Input Data size
7F6h - 7F7h Output I/O Length RO Output I/O size
7F8h - 7F9h Output DPRAM Length RO Number of output I/O bytes in dual port memory
7FAh - 7FBh Output Total Length RO Total Output Data size
7FCh - 7FDh
(reserved) -
剩余81页未读,继续阅读
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