SMBus 3.0 规范详解
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System Management Bus (SMBus) 是一种低带宽、低功耗的两线接口，用于在计算机系统内部或周边设备之间进行通信。SMBus 3.0 规范是该标准的一个版本，发布于2014年12月，由System Management Interface Forum (SMIF) 提供，并在www.powerSIG.org上可以获取。
SMBus 3.0 规范的主要特点和改进包括：
1. **速度提升**：相较于前代版本，SMBus 3.0 提高了数据传输速率。这使得它更适合高速通信需求，提高了系统的响应时间和效率。
2. **增强的错误检测和纠正机制**：新规范可能包含了更高级别的错误检测和报告功能，以确保数据的准确性和系统的稳定性。
3. **兼容性**：尽管增加了新特性，SMBus 3.0 仍然保持与早期版本的向后兼容性，这意味着旧的SMBus设备可以与支持SMBus 3.0的系统一起工作。
4. **电源管理**：SMBus 3.0 可能包含改进的电源管理特性，如动态功率调整，以优化能源效率并减少系统能耗。
5. **安全性**：可能增强了安全特性，如加密和身份验证，以保护数据在传输过程中的安全。
6. **协议扩展**：SMBus 3.0 可能定义了新的命令和协议，以支持更多的设备类型和应用场景，如传感器、电池管理系统、温度监控和其他系统管理功能。
7. **硬件和软件接口**：规范可能更新了硬件接口定义，以支持更快的数据传输，同时也可能改进了软件接口，简化了驱动程序开发和设备集成。
8. **标准化**：SMBus 3.0 的发布强调了对标准的遵循，以避免侵权问题，并确保所有实现都符合统一的标准。
9. **责任限制**：规范明确指出，其提供者不承担任何直接或间接损失的责任，包括但不限于利润损失、使用损失、偶然或间接损害，无论是否事先通知。
SMBus 3.0 规范的使用者应注意，虽然它旨在提高性能和功能，但在实际应用中，可能存在第三方专利侵权的风险，因此在实现规范时应谨慎评估和处理潜在的法律问题。
SMBus 3.0 是一种针对系统管理的高效、低功耗通信协议，它在保留与旧版兼容性的前提下，提升了速度和功能，以适应现代计算平台的需求。
System Management Bus (SMBus) Specification Version 3.0
Symbol
Meaning
A “don’t care” bit that may have a value of
0 or 1 sent from the slave device to the host
when responding to the Alert Response
Address (ARA)
Figure 1
shows an example of a generic SMBus transaction data structure. Note
the START and STOP conditions are transitions, not bits, and are shown without a
bit count number above the symbol. When shown in a transaction diagram, the
REPEATED START is also a transition, not a bit, and is shown without a bit count
above the symbol.
Figure 1: Generic transaction diagram
3. General Characteristics
SMBus is a two-wire bus. Multiple devices, both bus masters and bus slaves, may be
connected to a SMBus segment. Generally, a bus master device initiates a bus
transfer between it and a single bus slave and provides the clock signals. One
exception to this rule, detailed later, is during initial bus setup when a single master may
initiate transactions with multiple slaves simultaneously. Another exception is during a
ZONE WRITE when a master may be sending data to multiple slaves simultaneously. A
bus slave device can receive data provided by the master or it can provide data to the
master.
Only one device may master the bus at any time. Since more than one device may
attempt to take control of the bus as a master, SMBus provides an arbitration
mechanism that relies on the wired-AND connection of all SMBus device interfaces to
the SMBus.
This specification defines two classes of electrical characteristics, Low Power and
High Power. The first class, originally defined in the SMBus 1.0 and 1.1 specifications,
was designed primarily with Smart Batteries in mind, but could be used with other Low
Power devices. Version 2.0 of the specification introduced an alternative higher power
set of electrical characteristics. This class is appropriate for use when higher drive
capability is required, for example with SMBus devices on PCI add-in cards and for
connecting such cards across the PCI connector between each other and to SMBus
devices on the system board.
This version, Version 3.0, of the SMBus specification introduces operation at higher
bus speeds (400 kHz and 1 MHz) and adds new data protocols for reading or writing
32 bit and 64 bit values. This version also reduces the minimum nominal V
DD
from 3
volts to 1.8 volts.
Devices may be powered by the bus V
DD
or by another power source, V
BUS
, (as with, for
example, Smart Batteries) and will inter-operate as long as they adhere to the SMBus
electrical specifications for their class.
Figure 2
shows an example implementation of a
5 volt SMBus with devices powered by the bus V
DD
inter-operating with self-powered
devices.
X
1
S
Slave Address Wr A Data Byte A P
7 1 1 8
1
© 2014 System Management Interface Forum, Inc. 14 of 85
All Rights Reserved
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