MIPI I2C基本规范v1.1.1修正表（Errata01）

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MIP-I2C基本规范V1.1.1 是由MIPI Alliance于2021年6月9日发布的标准，用于定义增强型集成电路（Integrated Circuit）之间的接口。该规范旨在确保高性能、低功耗和可靠的数据传输在各种应用中得以实现。MIP-I2C是一种广泛应用于移动设备、相机模块、显示器等领域的高速串行总线接口。然而，随着技术的发展和实际应用中的反馈，可能存在一些错误或不完善之处。这个版本的规范附带了一个名为"Errata01"的文档，发布于2022年3月11日。Errata01列出了在V1.1.1版本中发现的问题和修正措施，包括但不限于数据传输的错误描述、接口兼容性问题以及潜在的性能瓶颈。实施者需要注意的重要事项有： 1. 重要提示：这份Errata文档列出的问题将在未来的规范更新中得到解决，因此实施者应参考最新的文档以避免基于过时信息进行设计。 2. 纠正措施：所有纠正措施必须遵循，这意味着在设计产品或电路板时，应采纳这些修订，以确保符合规范要求。 3. 定位修正：每个修正的位置在附带的MIP-I2C规范副本中都有标记，为了减少错误实施的风险，建议丢弃未经标记的旧版规范副本。 4. 修订后的规范效力：经过Errata修正的MIP-I2C规范仍被视为MIP-I2C标准，根据MIPI会员协议和章程，会员公司的权利和义务适用于这一修改后的规范。遵循这些指南，实施者可以确保他们的设计符合MIP-I2C V1.1.1规范，从而获得最佳的系统性能和互操作性。对于那些已经在生产或设计过程中使用的早期版本，及时更新至最新 Errata 版本是至关重要的，以避免因遗留问题可能导致的性能下降或功能失效。同时，与MIPI Alliance保持沟通，获取最新的技术支持和指导，可以帮助开发者在快速发展的技术环境中保持竞争力。

Specification for I3C Basic Version 1.1.1

09-Jun-2021

Public Release Edition

5.1.9.3.30 Multi-Lane Data Transfer Control (MLANE) .............................197

5.1.9.3.31 Set Bus Context (SETBUSCON) ................................................204

5.1.9.4 Direct CCCs and Group Addresses .................................................................207

5.1.10 Error Detection and Recovery Methods for SDR ........................................................... 209

5.1.10.1 SDR Error Detection and Recovery Methods for I3C Target Devices ............209

5.1.10.1.1 Error Type TE0 ............................................................................210

5.1.10.1.2 Error Type TE1 ............................................................................ 211

5.1.10.1.3 Error Type TE2 ............................................................................ 211

5.1.10.1.4 Error Type TE3 ............................................................................ 211

5.1.10.1.5 Error Type TE4 ............................................................................ 211

5.1.10.1.6 Error Type TE5 ............................................................................212

5.1.10.1.7 Error Type TE6 (Optional) ..........................................................212

5.1.10.1.8 Error Type DBR (Optional) .........................................................213

5.1.10.1.9 Optional Recovery Method for Error Types TE0 and TE1 ..........214

5.1.10.2 SDR Error Detection and Recovery Methods for I3C Controller Devices .....215

5.1.10.2.1 Error Type CE0 ...........................................................................215

5.1.10.2.2 Error Type CE1 (Optional) ..........................................................215

5.1.10.2.3 Error Type CE2 ...........................................................................216

5.1.10.2.4 Error Type CE3 ...........................................................................216

5.1.10.2.5 Controller Error Detection and Escalation Handling ..................217

5.1.10.2.6 Controller Stuck SDA Handling ..................................................218

5.1.10.2.7 Controller Recovery After a Crash or Unexpected Reset ............219

5.1.11 Target Reset .................................................................................................................... 220

5.1.11.1 Theory of Operation........................................................................................220

5.1.11.2 RSTACT CCC ................................................................................................222

5.1.11.3 Target Reset Pattern ........................................................................................222

5.1.11.4 Full/Chip Reset Behavior ................................................................................223

5.1.11.4.1 Primary Controller Behavior After Full/Chip Reset ....................224

5.1.11.5 Wake from Target Reset Behavior ..................................................................224

5.1.12 Monitoring Device Early Termination Capability ........................................................... 225

5.1.13 Device to Device(s) Tunneling ....................................................................................... 226

5.2 High Data Rate (HDR) Modes .................................................................................................... 227

5.2.1 HDR Common Flows and Framing ................................................................................ 229

5.2.1.1 HDR Exit Pattern and HDR Restart Pattern ...................................................229

5.2.1.1.1 HDR Exit Pattern ........................................................................229

5.2.1.1.2 HDR Restart Pattern ....................................................................230

5.2.1.1.3 HDR Exit Pattern Detector ..........................................................231

5.2.1.1.4 HDR Restart and Exit Pattern Detector .......................................233

5.2.1.1.5 Compatibility of HDR Pattern Detection and Ternary Modes ....234

5.2.1.2 CCC Framing in HDR Modes.........................................................................235

5.2.1.2.1 Elements, Framing and Modality ................................................238

5.2.1.2.2 Broadcast Address ACK ..............................................................246

5.2.1.2.3 Direct CCC ACK/NACK and Retry ............................................247

5.2.1.2.4 Implications for Device and Bus Configuration ..........................248

5.2.1.2.5 Implications for Multi-Lane ........................................................248

5.2.1.2.6 Implications for Group Addressing .............................................250

5.2.1.2.7 Bus Efficiency .............................................................................251

5.2.1.3 Transition to HDR Mode Transfer ..................................................................252

5.2.1.3.1 Entering the HDR Mode After ENTHDRx CCC ........................253

5.2.1.3.2 Next HDR Mode Transfer After HDR Restart Pattern ................254

Version 1.1.1 Specification for I3C Basic

09-Jun-2021

Public Release Edition

5.2.2 HDR Double Data Rate Mode (HDR-DDR) .................................................................. 255

5.2.2.1 HDR-DDR Overview .....................................................................................259

5.2.2.2 HDR-DDR Command Coding ........................................................................265

5.2.2.2.1 CCC Transmission in HDR-DDR Mode .....................................268

5.2.2.3 HDR-DDR Flow Control Elements ................................................................276

5.2.2.3.1 Command to Write Data to Target ...............................................276

5.2.2.3.2 Command to Read Data from Target ...........................................280

5.2.2.3.3 End of a Complete Data Frame Transfer .....................................284

5.2.2.3.4 HDR-DDR Early Transfer Termination Set-Up ..........................284

5.2.2.3.5 Controller Ends or Continues the Read Transfer .........................286

5.2.2.3.6 Target Ends or Continues the Write Transfer ..............................292

5.2.2.4 HDR-DDR Error Detection ............................................................................298

5.2.2.5 HDR-DDR CRC-5 Algorithm.........................................................................299

5.2.3 HDR Ternary Modes (HDR-TSP / HDR-TSL) ............................................................... 300

5.2.4 HDR Bulk Transport Mode (HDR-BT) .......................................................................... 301

5.2.4.1 SDA Lane Bit Packing: Data Bytes (Commands, Data, CRC) .......................304

5.2.4.2 SDA Lane Bit Packing: Transition Bytes ........................................................305

5.2.4.3 HDR-BT Mode Structured Protocol Elements ...............................................306

5.2.4.3.1 Header Block ...............................................................................307

5.2.4.3.2 Data Blocks .................................................................................309

5.2.4.3.3 CRC Block ..................................................................................310

5.2.4.3.4 Data Block Delay Mechanism .....................................................315

5.2.4.3.5 Performance ................................................................................317

5.2.4.4 CCC Transmission in HDR-BT Mode ............................................................318

5.2.4.4.1 HDR-BT CCC Header Block ......................................................320

5.2.4.4.2 HDR-BT CCC Data Block ..........................................................321

5.2.4.4.3 HDR-BT CRC Block ..................................................................321

5.2.4.4.4 HDR-BT CCC Indicator Block ACK ..........................................322

5.2.4.4.5 HDR-BT CCC Write Segment ....................................................322

5.2.4.4.6 HDR-BT CCC Read Segment .....................................................323

5.2.4.4.7 HDR-BT CCC End Procedures ...................................................323

5.2.4.5 Options ............................................................................................................326

5.2.4.6 Diagrams .........................................................................................................327

5.2.4.7 Transfer Flow Control .....................................................................................333

5.3 Multi-Lane (ML) Data Transfer .................................................................................................. 335

5.3.1 ML Data Transfer Setup .................................................................................................. 336

5.3.1.1 ML Device Configuration ...............................................................................336

5.3.1.1.1 ML Devices with Group Addresses .............................................338

5.3.1.1.2 ML Devices with Multiple Dynamic Addresses ..........................341

5.3.1.2 The ML Frame ................................................................................................343

5.3.2 ML Frame Formats ......................................................................................................... 344

5.3.2.1 SDR Based ML Frame Formats ......................................................................344

5.3.2.2 HDR-DDR Based ML Frame Formats ...........................................................344

5.3.2.3 HDR-TSP Based ML Frame Formats .............................................................344

5.3.2.4 HDR-BT Based ML Frame Formats ...............................................................345

5.3.2.4.1 HDR-BT Codings and Interoperability for CCCs .......................349

5.3.2.4.2 HDR-BT DUAL Coding .............................................................357

5.3.2.4.3 HDR-BT QUAD Coding .............................................................358

6 I3C Electrical Specifications .................................................................................................. 359

6.1 DC I/O Characteristics ................................................................................................................ 359

6.2 Timing Specification ................................................................................................................... 364

Specification for I3C Basic Version 1.1.1

09-Jun-2021

Public Release Edition

Annex A I3C Communication Format Details ......................................................................... 385

A.1 I3C CCC Transfers ...................................................................................................................... 385

A.2 I3C Private Write and Read Transfers ......................................................................................... 386

A.3 Legacy I

C Write and Read Transfers on the I3C Bus ................................................................ 388

A.4 Dynamic Address and Enter HDR ............................................................................................... 390

Annex B SDR Mode Error Type Origins ................................................................................. 393

B.1 Error Types in I3C CCC Transfers .............................................................................................. 393

B.2 Error Types in I3C Private Read and Write Transfers ................................................................. 394

B.3 Error Types in Dynamic Address Arbitration .............................................................................. 396

Annex C I3C Controller FSMs ................................................................................................ 397

Annex D Typical I3C Protocol Communications ..................................................................... 405

D.1 Typical SDR Private Read ........................................................................................................... 405

D.2 Typical Direct CCC in SDR Mode .............................................................................................. 406

D.3 Typical Broadcast CCC in SDR Mode ........................................................................................ 407

D.4 Typical HDR-DDR Read ............................................................................................................. 408

D.5 Typical HDR-TSL Read .............................................................................................................. 408

D.6 Typical HDR-TSP Read .............................................................................................................. 408

D.7 Typical HDR-BT Read ................................................................................................................ 409

Annex E MIPI I3C Basic Specification Supplemental Patent Licensing Terms ...................... 411

Attachment A ................................................................................................................................... 413

Annex F I3C Basic Development Companies ......................................................................... 415

Version 1.1.1 Specification for I3C Basic

09-Jun-2021

Public Release Edition

Figures

Figure 1 I3C System Diagram ......................................................................................................................... 3

Figure 2 I3C vs. I

C FM+ Data Blocks Bit Rates in Mbps (12.5 MHz Clock) ............................................... 5

Figure 3 I3C vs. I

C FM+ 1 kB Effective Data Transfer Times in Ms ............................................................ 6

Figure 4 I3C vs. I2C FM+ Energy per 1 kB Effective Data Block, in mJ ....................................................... 6

Figure 5 I3C Multi-Lane Effective Bit Rates, in Mbps ................................................................................... 7

Figure 6 Example of Data Traffic on the I3C Bus ......................................................................................... 18

Figure 7 I3C Communication Flow ............................................................................................................... 19

Figure 8 I3C Controller Device Block Diagram ............................................................................................ 22

Figure 9 I3C Target Device Block Diagram .................................................................................................. 25

Figure 10 I3C Bus with I

C Devices and I3C Devices .................................................................................. 30

Figure 11 I3C Minimal Bus with I3C Target Devices ................................................................................... 31

Figure 12 Address Header Comparison ......................................................................................................... 38

Figure 13 Address Arbitration During Header ............................................................................................... 47

Figure 14 Transition from Address ACK to Mandatory Byte During IBI ..................................................... 53

Figure 15 Transition from IBI Address NACK to Repeated START or STOP .............................................. 54

Figure 16 Controller Clock Stalling in ACK Phase ....................................................................................... 60

Figure 17 Controller Clock Stalling in Write Parity Bit ................................................................................ 60

Figure 18 Controller Clock Stalling in T-Bit Before Next Read Data ........................................................... 61

Figure 19 Controller Clock Stalling in T-Bit Before STOP ........................................................................... 61

Figure 20 Controller Clock Stalling in Low T-Bit Before Repeated START ................................................ 62

Figure 21 Controller Clock Stalling in High T-Bit Before Repeated START ................................................ 62

Figure 22 Controller Clock Stalling in High T-Bit Before Repeated START and STOP .............................. 63

Figure 23 Controller Clock Stalling in Dynamic Address First Bit ............................................................... 63

Figure 24 Bus Condition Timing ................................................................................................................... 65

Figure 25 Dynamic Address Assignment Transaction ................................................................................... 71

Figure 26 IBI Sequence with Mandatory Data Byte ...................................................................................... 83

Figure 27 Pre-Handoff Steps Flow ................................................................................................................ 90

Figure 28 Graphical Representation of Async Mode 0 Timestamp Interpolation ....................................... 104

Figure 29 Example of Asynchronous Mode 0 Timestamp Data Transfer .................................................... 106

Figure 30 CCC Broadcast General Frame Format ....................................................................................... 111

Figure 31 CCC Direct General Frame Format............................................................................................. 111

Figure 32 ENEC/DISEC Format 1: Direct .................................................................................................. 125

Figure 33 ENEC/DISEC Format 2: Broadcast ............................................................................................ 125

Figure 34 ENTASx Format 1: Direct ........................................................................................................... 127

Figure 35 ENTASx Format 2: Broadcast ..................................................................................................... 128

Figure 36 RSTDAA Format ........................................................................................................................ 129

Figure 37 ENTDAA Format ........................................................................................................................ 129

Figure 38 Direct SETMWL/GETMWL Format .......................................................................................... 130

Figure 39 Broadcast SETMWL Format ....................................................................................................... 131

Figure 40 Direct SETMRL/GETMRL Format ............................................................................................ 132

Figure 41 Broadcast SETMRL Format ........................................................................................................ 133

Figure 42 DEFTGTS Format ....................................................................................................................... 134

Figure 43 ENTTM Format .......................................................................................................................... 136

Specification for I3C Basic Version 1.1.1

09-Jun-2021

Public Release Edition

Figure 44 SETDASA Format 1: Primary ..................................................................................................... 138

Figure 45 SETDASA Format 2: Point-to-Point ........................................................................................... 139

Figure 46 SETNEWDA Format .................................................................................................................. 140

Figure 47 GETPID Format .......................................................................................................................... 141

Figure 48 GETBCR Format ........................................................................................................................ 142

Figure 49 GETDCR Format ........................................................................................................................ 143

Figure 50 GETSTATUS Format 1 ............................................................................................................... 144

Figure 51 GETSTATUS Format 2 ............................................................................................................... 147

Figure 52 GETSTATUS Format 2 with Defining Byte PRECR .................................................................. 149

Figure 53 GETACCCR Format 1: Accepted ............................................................................................... 151

Figure 54 GETACCCR Format 2: Not Accepted ........................................................................................ 151

Figure 55 GETACCCR Format 3: Incorrect Cancel .................................................................................... 151

Figure 56 SETBRGTGT Format ................................................................................................................. 152

Figure 57 Components of Clock-to-Data Turnaround Delay (t

SCO

) ............................................................. 155

Figure 58 GETMXDS Format 1: Without Turnaround ............................................................................... 157

Figure 59 GETMXDS Format 2: With Turnaround ..................................................................................... 157

Figure 60 GETMXDS Format 3: With Defining Byte ................................................................................ 159

Figure 61 GETMXDS Format 3 With Defining Byte CRHDLY ................................................................. 161

Figure 62 GETCAPS Format 1 ................................................................................................................... 163

Figure 63 GETCAPS Format 2 ................................................................................................................... 168

Figure 64 GETCAPS Format 2 with Defining Byte TESTPAT ................................................................... 170

Figure 65 GETCAPS Format 2 with Defining Byte CRCAPS .................................................................... 172

Figure 66 GETCAPS Format 2 with Defining Byte DBGCAPS ................................................................ 174

Figure 67 GETCAPS Format 2 with Defining Byte VTCAPS .................................................................... 176

Figure 68 SETROUTE Format .................................................................................................................... 179

Figure 69 Example Routing Device ............................................................................................................ 180

Figure 70 SETXTIME Format 1: Broadcast ............................................................................................... 181

Figure 71 SETXTIME Format 2: Direct ..................................................................................................... 182

Figure 72 GETXTIME Format .................................................................................................................... 183

Figure 73 SETAASA Format ....................................................................................................................... 185

Figure 74 ENDXFER Format 1: Broadcast ................................................................................................. 186

Figure 75 ENDXFER Format 2: Direct ....................................................................................................... 187

Figure 76 RSTACT Format 1: Broadcast .................................................................................................... 189

Figure 77 RSTACT Format 2: Direct Write ................................................................................................ 190

Figure 78 RSTACT Format 3: Direct Read ................................................................................................. 190

Figure 79 SETGRPA Format ....................................................................................................................... 193

Figure 80 RSTGRPA Format 1: Direct ........................................................................................................ 194

Figure 81 Resetting a Group Address with the RSTGRPA Direct CCC ...................................................... 195

Figure 82 RSTGRPA Format 2: Broadcast .................................................................................................. 195

Figure 83 DEFGRPA Format....................................................................................................................... 196

Figure 84 MLANE Format 1: Broadcast ..................................................................................................... 197

Figure 85 MLANE Format 2: Direct ........................................................................................................... 198

Figure 86 MLANE Direct GET Version of SET/GET CCC (SDR Mode Only) ......................................... 198

Figure 87 SETBUSCON Format ................................................................................................................. 205

Figure 88 Example Waveform for Error Type TE0 ..................................................................................... 210

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