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Version 1.1.1 Specification for I3C Basic
09-Jun-2021
Copyright © 2016–2021 MIPI Alliance, Inc. vii
Public Release Edition
5.2.2 HDR Double Data Rate Mode (HDR-DDR) .................................................................. 255
5.2.2.1 HDR-DDR Overview .....................................................................................259
5.2.2.2 HDR-DDR Command Coding ........................................................................265
5.2.2.2.1 CCC Transmission in HDR-DDR Mode .....................................268
5.2.2.3 HDR-DDR Flow Control Elements ................................................................276
5.2.2.3.1 Command to Write Data to Target ...............................................276
5.2.2.3.2 Command to Read Data from Target ...........................................280
5.2.2.3.3 End of a Complete Data Frame Transfer .....................................284
5.2.2.3.4 HDR-DDR Early Transfer Termination Set-Up ..........................284
5.2.2.3.5 Controller Ends or Continues the Read Transfer .........................286
5.2.2.3.6 Target Ends or Continues the Write Transfer ..............................292
5.2.2.4 HDR-DDR Error Detection ............................................................................298
5.2.2.5 HDR-DDR CRC-5 Algorithm.........................................................................299
5.2.3 HDR Ternary Modes (HDR-TSP / HDR-TSL) ............................................................... 300
5.2.4 HDR Bulk Transport Mode (HDR-BT) .......................................................................... 301
5.2.4.1 SDA Lane Bit Packing: Data Bytes (Commands, Data, CRC) .......................304
5.2.4.2 SDA Lane Bit Packing: Transition Bytes ........................................................305
5.2.4.3 HDR-BT Mode Structured Protocol Elements ...............................................306
5.2.4.3.1 Header Block ...............................................................................307
5.2.4.3.2 Data Blocks .................................................................................309
5.2.4.3.3 CRC Block ..................................................................................310
5.2.4.3.4 Data Block Delay Mechanism .....................................................315
5.2.4.3.5 Performance ................................................................................317
5.2.4.4 CCC Transmission in HDR-BT Mode ............................................................318
5.2.4.4.1 HDR-BT CCC Header Block ......................................................320
5.2.4.4.2 HDR-BT CCC Data Block ..........................................................321
5.2.4.4.3 HDR-BT CRC Block ..................................................................321
5.2.4.4.4 HDR-BT CCC Indicator Block ACK ..........................................322
5.2.4.4.5 HDR-BT CCC Write Segment ....................................................322
5.2.4.4.6 HDR-BT CCC Read Segment .....................................................323
5.2.4.4.7 HDR-BT CCC End Procedures ...................................................323
5.2.4.5 Options ............................................................................................................326
5.2.4.6 Diagrams .........................................................................................................327
5.2.4.7 Transfer Flow Control .....................................................................................333
5.3 Multi-Lane (ML) Data Transfer .................................................................................................. 335
5.3.1 ML Data Transfer Setup .................................................................................................. 336
5.3.1.1 ML Device Configuration ...............................................................................336
5.3.1.1.1 ML Devices with Group Addresses .............................................338
5.3.1.1.2 ML Devices with Multiple Dynamic Addresses ..........................341
5.3.1.2 The ML Frame ................................................................................................343
5.3.2 ML Frame Formats ......................................................................................................... 344
5.3.2.1 SDR Based ML Frame Formats ......................................................................344
5.3.2.2 HDR-DDR Based ML Frame Formats ...........................................................344
5.3.2.3 HDR-TSP Based ML Frame Formats .............................................................344
5.3.2.4 HDR-BT Based ML Frame Formats ...............................................................345
5.3.2.4.1 HDR-BT Codings and Interoperability for CCCs .......................349
5.3.2.4.2 HDR-BT DUAL Coding .............................................................357
5.3.2.4.3 HDR-BT QUAD Coding .............................................................358
6 I3C Electrical Specifications .................................................................................................. 359
6.1 DC I/O Characteristics ................................................................................................................ 359
6.2 Timing Specification ................................................................................................................... 364