Verilog金标准参考指南

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"Verilog Golden Reference Guide 是一份深入且实用的Verilog硬件描述语言参考资料，由Doulous公司编撰，适用于硬件设计者快速查阅Verilog语法、语义、综合和应用。" Verilog是一种广泛使用的硬件描述语言，用于数字系统的设计、验证和综合。这份Golden Reference Guide详细介绍了Verilog的关键概念，它不是 IEEE 标准Verilog Language Reference Manual的替代品，而是作为一个方便的速查工具，提供了简洁的答案和实用的信息。在本书中，读者可以找到以下关键知识点： 1. **语法**：Verilog的基础语法结构包括模块定义、变量声明、运算符、赋值语句等。例如，如何定义一个基本的模块，声明不同类型的变量（reg、wire等），以及如何使用各种逻辑和算术运算符。 2. **语义**：理解Verilog代码在硬件层面上的行为至关重要。这涉及到进程（processes）、时序控制（clocks and timing）、并行与串行执行的概念，以及如何通过非阻塞和阻塞赋值来管理同步和异步行为。 3. **综合**：Verilog的一个重要应用是将描述转化为可实现的硬件电路。本书会解释如何编写可综合的代码，包括使用结构化设计方法、避免综合陷阱，以及优化设计以提高效率。 4. **验证**：Verilog也用于验证设计的正确性。书中可能涵盖测试平台（testbench）的构建，边界扫描测试（boundary scan testing），以及断言（assertions）和覆盖度测量（coverage metrics）等验证技术。 5. **实例应用**：书中可能包含大量示例，涵盖了从简单的逻辑门到复杂的处理器核的设计，帮助读者理解和应用Verilog解决实际问题。 6. **工具使用**：Verilog的实现离不开特定的EDA工具，如Synopsys的Verilog-XL。指南可能会介绍如何与这些工具交互，进行仿真、综合和后布局布线。 7. **设计模式和最佳实践**：书中可能会讨论常见的Verilog设计模式，以及如何遵循良好的编程习惯，以提高代码的可读性和可维护性。 8. **标准库和IP**：Verilog有丰富的预定义模块和接口，如PCI、UART等，书中可能会介绍如何利用这些标准库加速设计过程。 9. **版本差异**：尽管Verilog Golden Reference Guide基于Verilog-XL商标，但Verilog语言随着时间发展已有多次更新（如Verilog 2001、2005、SystemVerilog等）。指南可能对比不同版本间的差异，并提供相应指导。 Verilog Golden Reference Guide 是一个强大的参考资料，对那些需要日常使用Verilog进行硬件设计和验证的专业人士来说，是一份不可或缺的桌面手册。

A statement which conditionally executes at most one branch, depending on

the value of the case expression.

Syntax

CaseKeyword

(

Expression

)

Expression,...

Statement

{Expression may be variable}

Expression,...

Statement

... {Any number of cases}

[default [:]

Statement

] {Need not be at the end}

endcase

CaseKeyword =

{either} case casex casez

Where

See Statement.

Rules

Xs and Zs in a casex statement, and Zs in a casez statement mean “don’t

care”.

One default statement at most may be included. It is executed if no label

expressions match the case expression. (A ‘label’ is an expression or a

comma-separated list of expressions on the left of a colon, or the reserved

word default, which may or may not be followed by a colon.)

Where a label is a comma-separated list of two or more expressions, the label

is matched if the case expression matches any one of the label expressions.

If no label expressions match the case expression and there is no default

statement, the case statement has no effect.

Gotchas!

If more than one statement is to be executed for a particular label, the

statements must be enclosed in a begin-end or fork-join block.

A branch is only executed if the corresponding label is the first one to match

the case expression. Case labels need not be mutually exclusive, so a

Verilog compiler will not report an error where the same label has erroneously

been repeated.

The syntax of a casex or casez statement ends with the reserved word

endcase, not endcasex or endcasez.

An X or Z in the casex expression or a Z in a casez expression is matched

with any value in a case label. This may give confusing simulation results.

Synthesis

Assignments within case statements generally synthesize to multiplexers. If

variables (i.e. registers or nets) are used for case labels, priority encoders

may be synthesized.

Case

Coding standards are divided into two categories. Lexical coding standards,

which control text layout, naming conventions and commenting, are intended

to improve readability and ease of maintenance. Synthesis coding standards,

which control Verilog style, are intended to avoid common synthesis pitfalls

and find synthesis errors early in the design flow.

The following lists of coding standards will need to be modified according to

the choice of tools and personal preferences.

Lexical Coding Standards

Limit the contents of each Verilog source file to one module, and do not split

modules across files.

Source file names should relate to the file contents (e.g. ModuleName.v).

Write only one declaration or statement per line.

Use indentation as shown in the examples.

Be consistent about the case of user defined names (e.g. first letter a capital).

User defined names should be meaningful and informative, although local

names (e.g. loop variables) may be terse.

Write comments to explain (not duplicate) the Verilog code. It is particularly

important to comment interfaces (e.g. module parameters, ports, task and

function arguments).

Use parameters or `define macros wherever possible, instead of directly

embedding literal numbers and strings in declarations and statements.

Synthesis Coding Standards

Partition the design into small functional blocks, and use a behavioural style

for each block. Avoid gate level descriptions except for critical parts of the

design.

Have a well defined clocking strategy, and implement that strategy explicitly in

Verilog (e.g. single clock, multi-phase clocks, gated clocks, multiple clock

domains). Ensure that clock and reset signals in Verilog are clean (i.e. not

generated from combinational logic or unintentionally gated).

Have a well defined (manufacturing) testing strategy, and code up the Verilog

appropriately (e.g. all flipflops resettable, test access from external pins, no

functional redundancy).

Every Verilog always should conform to one of the standard synthesizable

process templates (see

Always

An always describing combinational and latched logic must have all of the

inputs in the event control list at the top of the always.

A combinational always must not contain incomplete assignments, i.e. all

outputs must be assigned for all combinations of input values.

An always describing combinational and latched logic must not contain

feedback, i.e. registers assigned as outputs from the always must not be

read as inputs to the always.

Coding Standards

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