IEEE Std 1801-2015
IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems
Copyright © 2016 IEEE. All rights reserved.
driver: The source or drain of a transistor, if the drain or source is connected to a power rail; a
complementary metal oxide semiconductor (CMOS) inverter that continually connects a node to power or
ground; any component that sets the value of its output via a transistor or inverter; a constant assignment;
any combinational logic including a buffer of any kind; any sequential logic; or any hardware description
language (HDL) construct(s) that synthesize(s) to such combinational or sequential logic.
driver supply: For a driver that is a transistor, the supply connected to its source or drain; for a driver that
is an inverter, the pair of supplies connected to the source/drain of the transistor pair comprising the
inverter; or for an output of an active component, the related supply set of that output.
electrically equivalent: For supply ports/nets, connected (whether the connections are evident or not in
the design) without any intervening switches, and therefore have the same value at all times from the
perspective of any load; for supply sets/set handles, consisting of a set of electrically equivalent supply
nets for each required function.
equivalent: A pair of supply nets, a pair of supply sets or a pair of logic nets that are considered to be
interchangeable for certain purposes. See also: electrically equivalent; functionally equivalent.
erroneous: A usage that is likely to lead to an error in the design, but that tools may not be able to detect
and report.
extent (of a domain): The set of instances that comprise a power domain.
fanout domain (of a given port to which a given strategy applies): The power domain containing any of
the following: receiving logic for that port, or a leaf-level cell instance HighConn input port that is
connected to the given port, or a design top module LowConn output port that is connected to the given
port.
feedthrough: A direct connection between two ports on the interface of a power domain, where the
connection involves two ports on the upper boundary, or two ports on the lower boundary, or one of each;
also, a direction connection between two ports of the same leaf-level instance.
feedthrough port: A port on the interface of a power domain that is part of a feedthrough through that
domain, or a port on the interface of a leaf-level instance that is part of a feedthrough through that
instance.
fine grain switch: A power switch that is used to generate switched supply for a single library cell. This is
typically used to describe embedded macro power switches. This is identified using the attribute
switch_cell_type: fine_grain in Liberty and design attribute UPF_switch_cell_type fine_grain in
Unified Power Format (UPF) (see Table 4
).
functionally equivalent: Functioning identically from the perspective of any load, either as a result of
being electrically equivalent, or due to independent but parallel circuitry.
generate block: In the hardware description language (HDL) code, this represents a level of design
hierarchy, although a generate block is not itself an instance. After synthesis, generate blocks do not exist
as an independent level of hierarchy. It is illegal to create any Unified Power Format (UPF) objects in a
scope that corresponds to a generate block.
golden source: The design together with the constraint Unified Power Format (UPF) and the configuration
UPF.
hard macro: A block that has been completely implemented and can be used as it is in other blocks. This
can be modeled by an hardware description language (HDL) module for verification or as a library cell for
implementation.
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