STM32H743xI微控制器芯片手册：功能和规格概述

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"stm32h7芯片手册详解" stm32h7芯片是一款基于ARM Cortex-M7内核的微控制器单元（MCU），其具有强大的处理能力和丰富的外设资源。本文将对stm32h7芯片的手册进行详细的解读，涵盖其核心架构、存储器、安全机制、输入/输出端口和电源管理等方面。 **核心架构** stm32h7芯片基于ARM Cortex-M7内核，具有双精度浮点运算单元（FPU）和一级缓存（L1 cache），其中包括16KB的数据缓存和16KB的指令缓存。该芯片的主频率可达400MHz，具有856DMIPS的处理能力和2.14DMIPS/MHz的性能。 **存储器** stm32h7芯片具有丰富的存储器资源，包括： * 高达2MB的Flash存储器，支持读写操作 * 1MB的RAM，包括： + 192KB的TCM RAM（包括64KB的ITCM RAM和128KB的DTCM RAM），用于时间关键型应用 + 864KB的用户SRAM + 4KB的SRAM在备份域中 * 双模式四路SPI存储器接口，最高频率达133MHz * 灵活的外部存储器控制器，支持SRAM、PSRAM、SDRAM/LPSDR SDRAM和NOR/NAND Flash存储器，最高频率达133MHz **安全机制** stm32h7芯片具有强大的安全机制，包括： * ROP、PC-ROP和激活防tamper检测 * CRC计算单元，用于数据完整性检查 **输入/输出端口** stm32h7芯片具有丰富的输入/输出端口资源，包括： * 高达168个I/O端口，具有中断能力 **电源管理** stm32h7芯片具有三个独立的电源域，可以独立地控制和管理电源，包括： * 三个独立的电源域，可以独立地控制和管理电源 * 支持多种电源模式，包括正常模式、低功耗模式和休眠模式 stm32h7芯片是一款功能强大、资源丰富的微控制器单元，具有广泛的应用前景，包括工业控制、消费电子、医疗电子等领域。

Description STM32H743xI

16/231 DS12110 Rev 5

Operating temperatures

Ambient temperatures: –40 up to +85 °C

(4)

Junction temperature: –40 to + 125 °C

Package

LQFP100

TFBGA100

(5)

LQFP144

UFBGA

169

(5)

LQFP176

UFBGA

176+25

LQFP208

TFBGA

240+25

1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio

mode.

2. Since the LQFP100 package does not feature the PDR_ON pin (tied internally to V

), the minimum V

value for this

package is 1.71 V.

3. V

DDA

can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor)

and connecting PDR_ON pin to V

. Otherwise the supply voltage must stay above 1.71 V with the embedded power

voltage detector enabled.

4. The product junction temperature must be kept within the –40 to +125 °C temperature range.

5. This package is under development. Please contact STMicroelectronics for details.

Table 2. STM32H743xI features and peripheral counts (continued)

Peripherals

STM32H

743VI

STM32H

743ZI

STM32H

743AI

STM32H

743II

STM32H

743BI

STM32H

743XI

DS12110 Rev 5 17/231

STM32H743xI Description

Figure 1. STM32H743xI block diagram

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Functional overview STM32H743xI

18/231 DS12110 Rev 5

3 Functional overview

3.1 Arm

Cortex

-M7 with FPU

The Arm

Cortex

-M7 with double-precision FPU processor is the latest generation of Arm

processors for embedded systems. It was developed to provide a low-cost platform that

meets the needs of MCU implementation, with a reduced pin count and optimized power

consumption, while delivering outstanding computational performance and low interrupt

latency.

The Cortex

-M7 processor is a highly efficient high-performance featuring:

 Six-st

age dual-issue pipeline

 Dynamic branch prediction

 Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)

 64-bit AXI interface

 64-bit ITCM interface

 2x32-bit DTCM interfaces

The following memory interfaces are supported:

 Sep

arate Instruction and Data buses (Harvard Architecture) to optimize CPU latency

 Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM

accesses

 AXI Bus interface to optimize Burst transfers

 Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.

The processor supports a set of DSP instructions which allow efficient signal processing and

com

plex algorithm execution.

It also supports single and double precision FPU

(floating point unit) speeds up software

development by using metalanguage development tools, while avoiding saturation.

Figure 1 shows the general block diagram of the STM32H743xI family.

Note: Cortex

-M7 with FPU core is binary compatible with the Cortex

-M4 core.

3.2 Memory protection unit (MPU)

The memory protection unit (MPU) manages the CPU access rights and the attributes of the

system resources. It has to be programmed and enabled before use. Its main purposes are

to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by

a privileged task, but also to protect data processes or read-protect memory regions.

The MPU defines access rules for privileged accesses and user program accesses. It

llows defining up to 16 protected regions that can in turn be divided into up to 8

independent subregions, where region address, size, and attributes can be configured. The

protection area ranges from 32 bytes to 4 Gbytes of addressable memory.

When an unauthorized access is performed, a memory management exception is

enerated.

Functional overview STM32H743xI

20/231 DS12110 Rev 5

Error code correction (ECC)

Over the product lifetime, and/or due to external events such as radiations, invalid bits in

memories may occur. They can be detected and corrected by ECC. This is an expected

behavior that has to be managed at final-application software level in order to ensure data

integrity through ECC algorithms implementation.

SRAM data are protected by ECC:

 7 ECC bit

s are added per 32-bit word.

 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.

The ECC mechanism is based on the SECDED algor

ithm. It supports single-error correction

and double-error detection.

3.4 Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option

bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF

which includes:

 All Flash ad

dress space

 All RAM address space: ITCM, DTCM RAMs and SRAMs

 The System memory bootloader

The boot loader is located in non-user System me

mory. It is used to reprogram the Flash

memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32

microcontroller System memory Boot mode application note (AN2606) for details.

3.5 Power supply management

3.5.1 Power supply scheme

STM32H743xI power supply voltages are the following:

 V

= 1.62 to 3.6 V: external power supply for I/Os, provided externally through V

pins.

 V

DDLDO

= 1.62 to 3.6 V: supply voltage for the internal regulator supplying V

CORE

 V

DDA

= 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and

OPAMP.

 V

DD33USB and

DD50USB

can be supplied through the USB cable to generate the V

DD33USB

via the

USB internal regulator. This allows supporting a V

supply different from 3.3 V.

The USB regulator can be bypassed to supply directly V

DD33USB

if V

= 3.3 V.

 V

BAT

= 1.2 to 3.6 V: power supply for the V

domain when V

is not present.

 V

CAP

: V

CORE

supply voltage, which values depend on voltage scaling (0.7 V, 0.9 V,

1.0 V, 1.1 V or 1.2 V). They are configured through VOS bits in PWR_D3CR register.

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