BCM53101原厂网卡芯片七端口管理交换机详解

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标题"网卡芯片BCM53101原厂pdf文档"介绍了一款高度集成且经济高效的七端口10/100BASE-T/TX管理型以太网交换芯片——BCM53101M。该芯片由Broadcom公司开发，基于行业领先的ROBO架构设计，旨在提供高速、高效且全面的网络解决方案。 BCM53101M的特点包括： 1. 集成度高：作为一款单片65纳米CMOS设备，它集成了多种功能，如高速数据包缓冲器、PHY（物理层）收发器、媒体访问控制器（MAC）、地址管理和端口速率控制等，大大简化了系统设计。 2. 管理功能强大：作为一款管理型交换机，它支持端口级别的速率控制，允许根据连接设备的需求动态调整带宽，同时具备MAC控制PAUSE帧功能，确保与各种标准以太网和快速以太网设备兼容。 3. 应用广泛：BCM53101M不仅适用于下一代有线、xDSL、EPON/GPON网络的接入点，如宽带路由器和光纤到户（FTTH）设备，还特别适合中小企业（SOHO/SMB）环境中的网络部署。 4. 标准合规性：严格遵循IEEE 802.3和IEEE 802.3x标准，保证了产品的稳定性和互操作性。 5. 成本效益：由于其高度集成，可以降低系统总体成本，提高产品的性价比，对于寻求低成本、高性能网络解决方案的制造商来说是一个理想选择。 6. 技术优势：基于成熟的ROBO架构，意味着BCM53101M在长期的市场实践中已经经过验证，可靠性高，能够满足不同应用场景对性能和稳定性的要求。这份PDF文档详细列出了BCM53101M的各项特性和规格，对于了解和设计基于此芯片的网络设备具有重要参考价值。对于网络工程师、系统集成商和硬件开发商来说，深入研究这款芯片有助于他们优化网络设计，提升产品性能，并适应不断变化的市场需求。

CONFIDENTIAL FOR ZTE CORPORATION

8/9/2012 PJ87F

Table of Contents BCM53101M Preliminary Data Sheet

BROADCOM

December 2, 2011 • 53101M-DS05-R Page 16

Page 85h: WAN Interface (Port 5) External PHY MII Registers .................................................................258

Page 88h: IMP Port External PHY MII Registers Page Summary...............................................................258

Page 90h: BroadSync™ HD Registers .........................................................................................................259

BroadSync HD Enable Control Register (Page 90h, Address 00h–01h)................................................259

BroadSync HD Timestamp Report Control Register

(Page 90h, Address 02h) ..................................................................................................................260

BroadSync HD Maximum AV Packet Size Register

(Page 90h, Address 04h–05h) ..........................................................................................................260

BroadSync HD Time Base Register (Page 90h, Address 10h–13h) .......................................................260

BroadSync HD Timestamp Report Control Register (Page 90h, Address 14h–17h).............................261

BroadSync HD Slot Number and Tick Counter Register (Page 90h, Address 18h–1Bh).......................261

BroadSync HD Slot Adjustment Register (Page 90h, Address 1Ch–1Fh)..............................................262

BroadSync HD Class 5 Bandwidth Control Register (Page 90h, Address 30h–3Bh) .............................262

BroadSync HD Class 4 Bandwidth Control Register (Page 90h, Address 60h–6Bh) .............................263

BroadSync HD Egress Timestamp Register (Page 90h, Address 90h–A7h) ..........................................264

BroadSync HD Egress Timestamp Status Register (Page 90h, Address AFh) .......................................264

BroadSync HD Port AV Link Status Register (Page 90h, Address B0h–B1h).........................................265

Page 91h: Traffic Remarking Registers ......................................................................................................265

Traffic Remarking Control Register (Page 91h: Address 00h–03h)......................................................266

Egress Non-BroadSync HD Packet TC to PCP Mapping Register (Page 91h: Address 10h–57h)..........266

Global Registers..........................................................................................................................................267

SPI Data I/O Register (Global, Address F0h–F7h).................................................................................267

SPI Status Register (Global, Address FEh) ............................................................................................268

Page Register (Global, Address FFh) ....................................................................................................268

Section 9: Electrical Characteristics................................................................................ 269

Absolute Maximum Ratings .......................................................................................................................269

Recommended Operating Conditions........................................................................................................269

Electrical Characteristics ............................................................................................................................270

Section 10: Timing Characteristics ................................................................................. 273

Reset and Clock Timing ..............................................................................................................................273

MII/TMII Interface Timing..........................................................................................................................274

MII/TMII Input Timing..........................................................................................................................274

MII/TMII Output Timing.......................................................................................................................275

RMII Interface Timing.................................................................................................................................276

RMII Input/Output Timing ...................................................................................................................276

Reverse MII/TMII Interface Timing............................................................................................................277

CONFIDENTIAL FOR ZTE CORPORATION

8/9/2012 PJ87F

Table of Contents BCM53101M Preliminary Data Sheet

BROADCOM

December 2, 2011 • 53101M-DS05-R Page 17

Reverse MII/TMII Input Timing ............................................................................................................277

Reverse MII Output Timing..................................................................................................................278

RGMII Interface Timing ..............................................................................................................................279

RGMII Output Timing (Normal Mode) .................................................................................................279

RGMII Output Timing (Delayed Mode) ................................................................................................280

RGMII Input Timing (Normal Mode) ....................................................................................................281

RGMII Input Timing (Delayed Mode) ...................................................................................................282

MDC/MDIO Timing.....................................................................................................................................283

Serial LED Interface Timing ........................................................................................................................284

SPI Timings..................................................................................................................................................285

EEPROM Timing ..........................................................................................................................................286

Section 11: Thermal Characteristics............................................................................... 287

Section 12: Mechanical Drawing.................................................................................... 288

Section 13: Ordering Information .................................................................................. 289

CONFIDENTIAL FOR ZTE CORPORATION

8/9/2012 PJ87F

List of Figures BCM53101M Preliminary Data Sheet

BROADCOM

December 2, 2011 • 53101M-DS05-R Page 18

List of Figures

Figure 1: BCM53101E Functional Block Diagram ...............................................................................................2

Figure 2: QoS Program Flow.............................................................................................................................33

Figure 3: VLAN Table Organization...................................................................................................................38

Figure 4: Trunking.............................................................................................................................................40

Figure 5: Bucket Flow .......................................................................................................................................41

Figure 6: Mirror Filter Flow ..............................................................................................................................44

Figure 7: BroadSync HD Shaping and Scheduling .............................................................................................48

Figure 8: Address Table Organization...............................................................................................................50

Figure 9: Power State Diagram.........................................................................................................................59

Figure 10: IMP Packet Encapsulation Format...................................................................................................69

Figure 11: TXQ and Buffer Tag Structure..........................................................................................................81

Figure 12: MII/RvMII Port Connection .............................................................................................................84

Figure 13: Normal SPI Command Byte .............................................................................................................86

Figure 14: Fast SPI Command Byte...................................................................................................................86

Figure 15: SPI Serial Interface Write Operation ...............................................................................................87

Figure 16: SPI Serial Interface Read Operation ................................................................................................87

Figure 17: SPI Interface Without External PHY Device .....................................................................................88

Figure 18: Accessing External PHY Registers ....................................................................................................88

Figure 19: Normal Read Operation ..................................................................................................................90

Figure 20: Normal Read Mode to Check the SPIF Bit of SPI Status Register ....................................................91

Figure 21: Normal Read Mode to Setup the Accessed Register Page Value ....................................................91

Figure 22: Normal Read Mode to Set Up the Accessed Register Address Value (Dummy Read).....................92

Figure 23: Normal Read Mode to Check the SPI Status for Completion of Read .............................................92

Figure 24: Normal Read Mode to Obtain the Register Content.......................................................................93

Figure 25: Fast Read Operation........................................................................................................................94

Figure 26: Normal Read Mode to Check the SPIF Bit of SPI Status Register ....................................................95

Figure 27: Fast Read Mode to Set Up New Page Value....................................................................................95

Figure 28: Fast Read to Read the Register .......................................................................................................96

Figure 29: Normal Write Operation .................................................................................................................97

Figure 30: Normal Read Mode to Check the SPIF Bit of SPI Status Register ....................................................98

Figure 31: Normal Write to Set Up the Register Page Value............................................................................98

Figure 32: Normal Write to Write the Register Address Followed by Written Data........................................99

Figure 33: Serial EEPROM Connection .............................................................................................................99

Figure 34: EEPROM Programming Example ...................................................................................................100

Figure 35: Pseudo-PHY MII Register Definitions ............................................................................................103

CONFIDENTIAL FOR ZTE CORPORATION

8/9/2012 PJ87F

List of Figures BCM53101M Preliminary Data Sheet

BROADCOM

December 2, 2011 • 53101M-DS05-R Page 19

Figure 36: Pseudo-PHY MII Register 16: Register Set Access Control Bit Definition ......................................104

Figure 37: Pseudo-PHY MII Register 17: Register Set Read/Write Control Bit Definition ..............................104

Figure 38: Pseudo-PHY MII Register 18: Register Access Status Bit Definition ..............................................105

Figure 39: Pseudo-PHY MII Register 24: Access Register Bit Definition .........................................................105

Figure 40: Pseudo-PHY MII Register 25: Access Register Bit Definition .........................................................105

Figure 41: Pseudo-PHY MII Register 26: Access Register Bit Definition .........................................................106

Figure 42: Pseudo-PHY MII Register 27: Access Register Bit Definition .........................................................106

Figure 43: Read Access to the Register Set Using the Pseudo-PHY (PHYAD = 11110) MDC/MDIO Path .......107

Figure 44: Write Access to the Register Set Using the Pseudo-PHY (PHYAD = 11110) MDC/MDIO Path ......108

Figure 45: LED Interface Register Structure Diagram.....................................................................................111

Figure 46: LED Interface Block Diagram .........................................................................................................112

Figure 47: LED Circuit for Dual-Input Configuration/LED Output Pins ...........................................................113

Figure 48: Ball Location Diagram....................................................................................................................129

Figure 49: Reset and Clock Timing .................................................................................................................269

Figure 50: MII Input Timing ............................................................................................................................270

Figure 51: MIIOutput Timing ..........................................................................................................................271

Figure 52: Reverse MII Input Timing ..............................................................................................................272

Figure 53: Reverse MII Output Timing ...........................................................................................................273

Figure 54: MDC/MDIO Timing (Slave Mode)..................................................................................................274

Figure 55: Serial LED Interface Timing............................................................................................................275

Figure 56: SPI Timings, SS

Asserted During SCK High .....................................................................................276

Figure 57: SPI Timings, SS

Asserted During SCK Low ......................................................................................276

Figure 58: EEPROM Timing.............................................................................................................................277

Figure 59: BCM53101M Mechanical Drawing................................................................................................279

CONFIDENTIAL FOR ZTE CORPORATION

8/9/2012 PJ87F

List of Tables BCM53101M Preliminary Data Sheet

BROADCOM

December 2, 2011 • 53101M-DS05-R Page 20

List of Tables

Table 1: TC Decision Tree Summary .................................................................................................................36

Table 2: Reasons to Forward a Packet to the CPU ...........................................................................................37

Table 3: Bucket Bit Rate ...................................................................................................................................43

Table 4: Unicast Forward Field Definitions.......................................................................................................53

Table 5: Address Table Entry for Unicast Address............................................................................................53

Table 6: Multicast Forward Field Definitions ...................................................................................................54

Table 7: Address Table Entry for Multicast Address.........................................................................................54

Table 8: Behavior for Reserved Multicast Addresses .......................................................................................55

Table 9: Power-Saving Modes of the BCM53101M..........................................................................................59

Table 10: Enable EPHY Shadow Registers ........................................................................................................61

Table 11: Enable Auto Power-Down ................................................................................................................61

Table 12: Disable EPHY Shadow Registers........................................................................................................61

Table 13: Egress Broadcom Tag Format for Opcode = 000 (IMP to CPU).........................................................71

Table 14: Egress Broadcom Tag Format for Opcode = 001 (IMP to CPU).........................................................71

Table 15: Ingress Broadcom Tag for Opcode = 000 (CPU to IMP) ....................................................................72

Table 16: Ingress Broadcom Tag for Opcode = 001 (CPU to IMP) ....................................................................72

Table 17: Receive-Only Counters .....................................................................................................................73

Table 18: Transmit-Only Counters....................................................................................................................75

Table 19: Transmit/Receive Counters ..............................................................................................................76

Table 20: Directly Supported MIB Counters.....................................................................................................77

Table 21: Indirectly Supported MIB Counters ..................................................................................................79

Table 22: BCM53101M Supported MIB Extensions .........................................................................................80

Table 23: EEPROM Header Format.................................................................................................................102

Table 24: EEPROM Contents ..........................................................................................................................102

Table 25: MII Management Frame Format ....................................................................................................111

Table 26: LED Output Pins Per Port ................................................................................................................112

Table 27: Dual-Input Configuration/LED Outputs ..........................................................................................115

Table 28: I/O Signal Type Definitions .............................................................................................................116

Table 29: Signal Description ...........................................................................................................................116

Table 30: BCM53101 Signals by Ball...............................................................................................................124

Table 31: BCM53101 Signals by Name ...........................................................................................................128

Table 32: Global Page Register Map...............................................................................................................133

Table 33: Control Registers (Page 00h) ..........................................................................................................135

Table 34: Port Traffic Control Register Address Summary .............................................................................137

Table 35: Port Traffic Control Register (Page 00h: Address 00h–05h) ...........................................................137

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