ARMv8架构详解：A64与A32/T32新指令集概览

需积分: 14 133 浏览量更新于2024-07-19 收藏 475KB PDF 举报

ARMv8 Instruction Set Architecture (ISA) 是一个高级别概述文档，主要关注ARMv8架构的新特性，特别是针对64位（AArch64）状态下的A64指令集。这份文档不仅详细解释了A64指令集，还包括自ARMv7-A以来添加到A32和T32指令集中的新指令，这些指令在AArch32状态中也被广泛使用。A64指令集的介绍强调了推荐的架构级汇编语言表示法，以便于开发者理解和编写代码。 ARMv8架构是ARM公司的第六代处理器架构，它包含了对64位计算的强大支持，这使得它能够在更广泛的领域如服务器、数据中心、移动设备和嵌入式系统中发挥重要作用。A64指令集提供了更高的性能和效率，比如向量运算、内存访问优化、多线程处理等特性，对于现代高性能计算至关重要。文档PRD03-GENC-010197由ARM Limited发布，版权日期为2013年6月3日。该文档涵盖了以下关键知识点： 1. **A64指令集**：专为AArch64架构设计，旨在提供高性能计算能力，支持宽依赖性指令、向量/SIMD指令、内存操作符扩展和对内存安全特性的优化。 2. **A32和T32指令集增强**：在保留A32传统指令集的同时，引入了新的功能，以满足AArch32状态下的兼容性和性能需求。 3. **Assembly Language Notation**：文档提供了编写符合ARMv8标准的A64指令的推荐语法，这对于开发人员来说是至关重要的学习资源。 4. **版权和知识产权保护**：文档内容受版权保护，未经许可复制或实施可能会侵犯专利权。用户在使用时需确保遵循相应授权规定。 5. **关键词**：AArch64、A64、AArch32、A32、T32以及ARMv8，这些都是与文档内容紧密相关的术语，用于识别文档所讨论的特定技术领域。 ARMv8 Instruction Set Architecture文档为理解ARMv8架构的最新进展提供了全面指南，对于开发人员、系统架构师和硬件工程师来说，它是深入研究和实现高效、兼容64位ARM处理器的关键参考资料。

ARMv8 Instruction Set Overview

PRD03-GENC-010197

4 A64 ASSEMBLY LANGUAGE

4.1 Basic Structure

The letter W is shorthand for a 32-bit word, and X for a 64-bit extended word. The letter X (extended) is used rather

than D (double), since D conflicts with its use for floating point and SIMD “double-precision” registers and the T32

load/store “double-register” instructions (e.g. LDRD).

An A64 assembler will recognise both upper and lower-case variants of instruction mnemonics and register

names, but not mixed case. An A64 disassembler may output either upper or lower-case mnemonics and register

names. The case of program and data labels is significant.

The fundamental statement format and operand order follows that used by AArch32 UAL assemblers and

disassemblers, i.e. a single statement per source line, consisting of one or more optional program labels, followed

by an instruction mnemonic, then a destination register and one or more source operands separated by commas.

{label:*} {opcode {dest{, source1{, source2{, source3}}}}}

This dest/source ordering is reversed for store instructions, in common with AArch32 UAL.

The A64 assembly language does not require the ‘#’ symbol to introduce immediate values, though an assembler

must allow it. An A64 disassembler shall always output a ‘#’ before an immediate value for readability.

Where a user-defined symbol or label is identical to a pre-defined register name (e.g. “X0”) then if it is used in a

context where its interpretation is ambiguous – for example in an operand position that would accept either a

may be disambiguated by using it within an expression context, i.e. by placing it within parentheses and/or

prefixing it with an explicit ‘#’ symbol.

In the examples below the sequence “//” is used as a comment leader and ARMv8 assemblers are encouraged

to accept this syntax, though they may also support their legacy A32 and T32 comment syntax.

4.2 Instruction Mnemonics

An A64 instruction form can be identified by the following combination of attributes:

• The operation name (e.g. ADD) which indicates the instruction semantics.

• The operand container, usually the register type. An instruction writes to the whole container, but if it is not

the largest in its class, then the remainder of the largest container in the class is set to ZERO.

• The operand data subtype, where some operand(s) are a different size from the primary container.

• The final source operand type, which may be a register or an immediate value.

The container is one of:

Integer Class

W 32-bit integer

X 64-bit integer

SIMD Scalar & Floating Point Class

B 8-bit scalar

H 16-bit scalar & half-precision float

S 32-bit scalar & single-precision float

D 64-bit scalar & double-precision float

Q 128-bit scalar

ARMv8 Instruction Set Overview

PRD03-GENC-010197

The subtype is one of:

Load-Store / Sign-Zero Extend

B byte

SB signed byte

H halfword

SH signed halfword

W word

SW signed word

H High (dst gets top half)

N Narrow (dst < src)

L Long (dst > src)

W Wide (dst == src1, src1 > src2)

etc

These attributes are combined in the assembly language notation to identify the specific instruction form. In order

to retain a close look and feel to the existing ARM assembly language, the following format has been adopted:

In other words the operation name and subtype are described by the instruction mnemonic, and the container size

by the operand name(s). Where subtype is omitted, it is inherited from container.

In this way an assembler programmer can write an instruction without having to remember a multitude of new

mnemonics; and the reader of a disassembly listing can straightforwardly read an instruction and see at a glance

the type and size of each operand.

The implication of this is that the A64 assembly language overloads instruction mnemonics, and distinguishes

between the different forms of an instruction based on the operand register names. For example the ADD

instructions below all have different opcodes, but the programmer only has to remember one mnemonic and the

assembler automatically chooses the correct opcode based on the operands – with the disassembler doing the

reverse.

ADD W0, W1, W2 // add 32-bit register

ADD X0, X1, X2 // add 64-bit register

ADD X0, X1, W2, SXTW // add 64-bit extended register

ADD X0, X1, #42 // add 64-bit immediate

4.3 Condition Codes

In AArch32 assembly language conditionally executed instructions are represented by directly appending the

condition to the mnemonic, without a delimiter. This leads to some ambiguity which can make assembler code

difficult to parse: for example ADCS, BICS, LSLS and TEQ look at first glance like conditional instructions.

The A64 ISA has far fewer instructions which set or test condition codes. Those that do will be identified as

follows:

1. Instructions which set the condition flags are notionally different instructions, and will continue to be

identified by appending an ‘S’ to the base mnemonic, e.g. ADDS.

ARMv8 Instruction Set Overview

PRD03-GENC-010197

2. Instructions which are truly conditionally executed (i.e. when the condition is false they have no effect on

the architectural state, aside from advancing the program counter) have the condition appended to the

instruction with a '.' delimiter. For example B.EQ.

3. If there is more than one instruction extension, then the conditional extension is always last.

4. Instructions which are unconditionally executed, but use the condition flags as a source operand, will

specify the condition to test in their final operand position, e.g. CSEL Wd,Wm,Wn,NE

To aid portability an A64 assembler may also provide the old UAL conditional mnemonics, so long as they have

direct equivalents in the A64 ISA. However, the UAL mnemonics will not be generated by an A64 disassembler –

their use is deprecated in 64-bit assembler code, and may cause a warning or error if backward compatibility is

not explicitly requested by the programmer.

The full list of condition codes is as follows:

Encoding

Name

(& alias)

Meaning (integer) Meaning (floating point) Flags

0000 EQ

Equal Equal

Z==1

0001 NE

Not equal Not equal, or unordered

Z==0

0010

(CS)

Unsigned higher or same

(Carry set)

Greater than, equal, or unordered

C==1

0011

(CC)

Unsigned lower

(Carry clear)

Less than

C==0

0100 MI

Minus (negative) Less than

N==1

0101 PL

Plus (positive or zero) Greater than, equal, or unordered

N==0

0110 VS

Overflow set Unordered

V==1

0111 VC

Overflow clear Ordered

V==0

1000 HI

Unsigned higher Greater than, or unordered

C==1 && Z==0

1001 LS

Unsigned lower or same Less than or equal

!(C==1 && Z==0)

1010 GE

Signed greater than or equal Greater than or equal

N==V

1011 LT

Signed less than Less than or unordered

N!=V

1100 GT

Signed greater than Greater than

Z==0 && N==V

1101 LE

Signed less than or equal Less than, equal, or unordered

!(Z==0 && N==V)

1110 AL

1111 NV

†

Always Always

Any

†The condition code NV exists only to provide a valid disassembly of the ‘1111b’ encoding, and otherwise behaves

identically to AL.

ARMv8 Instruction Set Overview

PRD03-GENC-010197

4.4 Register Names

4.4.1 General purpose (integer) registers

The thirty one general purpose registers in the main integer register bank are named R0 to R30, with special

registers are used in a specific instruction form, they must be further qualified to indicate the operand data size (32

or 64 bits) – and hence the instruction’s data size.

The qualified names for the general purpose registers are as follows, where ‘n’ is the register number 0 to 30:

Size (bits)

32b 64b

Name

Wn Xn

Where register number 31 represents read zero or discard result (aka the “zero register”):

Size (bits)

32b 64b

Name

WZR XZR

Where register number 31 represents the current stack pointer:

Size (bits)

32b 64b

Name

WSP

In more detail:

• The names Xn and Wn refer to the same architectural register.

• There is no register named W31 or X31.

• For instruction operands where register 31 in interpreted as the 64-bit current stack pointer, it is

represented by the name SP. For operands which do not interpret register 31 as the stack pointer this

name shall cause an assembler error.

• The name WSP represents register 31 as the current stack pointer in a 32-bit context. It is provided only to

allow a valid disassembly, and should not be seen in correctly behaving 64-bit code.

• For instruction operands which interpret register 31 as the zero register, it is represented by the name XZR

in 64-bit contexts, and WZR in 32-bit contexts. In operand positions which do not interpret register 31 as

the zero register these names shall cause an assembler error.

• Where a mnemonic is overloaded (i.e. can generate different instruction encodings depending on the data

size), then an assembler shall determine the precise form of the instruction from the size of the first

some cases a register may have a different size (e.g. an address base register is always 64 bits), and a

source register may be smaller than the destination if it contains a word, halfword or byte that is being

widened by the instruction to 64 bits.

• The architecture does not define a special name for register 30 that reflects its special role as the link

Standard.

ARMv8 Instruction Set Overview

PRD03-GENC-010197

4.4.2 FP/SIMD registers

The thirty two registers in the FP/SIMD register bank named V0 to V31 are used to hold floating point

operands for the scalar floating point instructions, and both scalar and vector operands for the Advanced

SIMD instructions. As with the general purpose integer registers, when they are used in a specific instruction

form the names must be further qualified to indicate the data shape (i.e. the data element size and number of

elements or lanes) held within them.

Note however that the data type, i.e. the interpretation of the bits within each register or vector element –

integer (signed, unsigned or irrelevant), floating point, polynomial or cryptographic hash – is not described by

the register name, but by the instruction mnemonics which operate on them. For more details see the

Advanced SIMD description in §5.8.

4.4.2.1 SIMD scalar register

In Advanced SIMD and floating point instructions which operate on scalar data the FP/SIMD registers behave

similarly to the main general-purpose integer registers, i.e. only the lower bits are accessed, with the unused

high bits ignored on a read and set to zero on a write. The qualified names for scalar FP/SIMD names indicate

the number of significant bits as follows, where ‘n’ is a register number 0 to 31:

Size (bits)

8b 16b

32b 64b 128b

Name

Bn Hn Sn Dn Qn

4.4.2.2 SIMD vector register

When a register holds multiple data elements on which arithmetic will be performed in a parallel, SIMD

fashion, then a qualifier describes the vector shape: i.e. the element size, and the number of elements or

“lanes”. Where “bits



lanes” does not equal 128, the upper 64 bits of the register are ignored when read and

set to zero on a write.

The fully qualified SIMD vector register names are as follows, where ‘n’ is the register number 0 to 31:

Shape (bits



lanes)



8 8b



16 16b



16b



32b



32b



4 64b



1 64b



Name

Vn.8B Vn.16B Vn.4H Vn.8H Vn.2S Vn.4S Vn.1D Vn.2D

4.4.2.3 SIMD vector element

Where a single element from a SIMD vector register is used as a scalar operand, this is indicated by

appending a constant, zero-based “element index” to the vector register name, inside square brackets. The

number of lanes is not represented, since it is not encoded, and may only be inferred from the index value.

Size (bits)

8b 16b 32b 64b

Name

Vn.B[i] Vn.H[i] Vn.S[i] Vn.D[i]

However an assembler shall accept a fully qualified SIMD vector register name as in §4.4.2.2, so long as the

number of lanes is greater than the index value. For example the following forms will both be accepted by an

assembler as the name for the 32-bit element in bits <63:32> of SIMD register 9:

V9.S[1] standard disassembly

V9.2S[1] optional number of lanes

V9.4S[1] optional number of lanes

剩余114页未读，继续阅读

ijunjay

粉丝: 1
资源: 14

ARMv8架构详解：A64与A32/T32新指令集概览

Armv8-A Instruction Set Architecture.pdf

arm instruction set(arm 完整指令集）

Armv8-A Instruction Set Architecture_armv8指令集_ARMv8

《ARM Architecture Reference Manual ARMv8》

ARM Architecture Reference Manual for ARMv8-A

Arm Cortex-M Comparison Table_v3.pdf

ArmV9 Architecture Reference Manual for A-profile architecture

HC31_T4_RISCV-20190818-HotChips.pdf

Arm A64 Instruction Set Architecture Armv8, for Armv8-A architecture profile.pdf

Arm A64 Instruction Set Architecture.pdf

最新资源