Python的MyHDL：硬件设计与验证的优雅之选

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MyHDL是一个基于Python的硬件描述和验证语言工具包，它的目标是通过这种现代、优雅且简洁的语言特性来提升硬件设计师的设计能力。作为开源项目，MyHDL允许开发者利用Python的强大功能来设计和模拟复杂的硬件系统，使得高级建模变得更加直观和高效。在MyHDL中，核心概念是利用Python生成器来处理硬件并发性。生成器在MyHDL中扮演着类似于Verilog中的always块和VHDL中的进程的角色，但它们具有可恢复的特性，可以在执行过程中暂停并恢复。硬件模块在MyHDL中被设计成返回生成器的函数形式，这样可以轻松支持诸如任意层级结构、命名端口连接、实例数组以及条件实例化等高级特性。 Python的易用性和表达力使其成为建模的理想选择，尤其是在处理复杂系统时，能够快速开发原型并进行实验。与传统硬件设计流程相比，MyHDL提供了从Python代码到Verilog或VHDL代码的转换路径，这极大地简化了设计者的过渡过程，同时也保留了Python的灵活性和调试优势。使用MyHDL进行设计时，设计师可以通过定义函数来表示硬件组件的行为，这些函数内部包含生成器，使得代码既易于理解和维护，又能适应动态的硬件需求。此外，由于Python的交互式特性，设计师可以在设计过程中实时测试和迭代，提高了设计效率和准确性。 MyHDL不仅是一种硬件描述语言，更是一个结合了Python语言优势的工具套件，它将硬件设计与高级编程语言的优势相结合，为硬件工程师提供了一种新颖而强大的设计和验证手段。通过学习和实践MyHDL的例子和代码，设计师可以掌握如何利用Python的优雅语法和模块化结构，实现高效的硬件设计和验证工作。

formatstring % (arg1, arg2, ...)

where arg is a bool, int, intbv, enum, or a Signal of these types.

The formatstring contains ordinary characters and conversion specifiers as in Python. However,

the only supported conversion specifiers are %s and %d. Justification and width specification are

thus not supported.

Printing without a newline:

print arg1 ,

is not supported.

raise

This statement is mapped to statements that end the simulation with an error message.

return

yield

A yield expression is used to specify a sensitivity list. The yielded expression can be a

Signal, a signal edge as specified by MyHDL functions Signal.posedge or Signal.negedge, or

a tuple of signals and edge specifications. It can also be a delay() object.

while

The optional else clause is not supported.

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The following is a list of the built-in functions that are supported by the converter.

bool()

This function can be used to typecast an object explicitly to its boolean interpretation.

len()

For Signal and intbv objects, function len() returns the bit width.

int()

This function can be used to typecast an object explicitly to its integer interpretation.

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The convertor propagates comments under the form of Python docstrings.

Docstrings are typically used in Python to document certain objects in a standard way. Such

“official” docstrings are put into the converted output at appropriate locations. The convertor

supports official docstrings for the top level module and for generators.

Within generators, “nonofficial” docstrings are propagated also. These are strings (triple quoted by

convention) that can occur anywhere between statements.

Regular Python comments are ignored by the Python parser, and they are not present in the parse

tree. Therefore, these are not propagated. With docstrings, you have an elegant way to specify

which comments should be propagated and which not.

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Lists of signals are useful for many purposes. For example, they make it easy to create a repetitive

structure. Another application is the description of memory behavior.

The convertor output is non-hierarchical. That implies that all signals are declared at the top-level

in VHDL or Verilog (as VHDL signals, or Verilog regs and wires.) However, some signals that are

a list member at some level in the MyHDL design hierarchy may be used as a plain signal at a

lower level. For such signals, a choice has to be made whether to declare a Verilog memory or

VHDL array, or a number of plain signal names.

If possible, plain signal declarations are preferred, because Verilog memories and arrays have

some restrictions in usage and tool support. This is possible if the list syntax is strictly used

outside generator code, for example when lists of signals are used to describe structure.

Conversely, when list syntax is used in some generator, then a Verilog memory or VHDL array will

be declared. The typical example is the description of RAM memories.

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Complex designs often have many signals that are passed to different levels of hierarchy.

Typically, many signals logically belong together. This can be modelled by an interface: an object

that has a number of Signal objects as its attributes. Grouping signals into an interface simplifies

the code, improves efficiency, and reduces errors.

The convertor supports interface using hierarchical name expansion and name mangling.

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Name assignment in Python is a different concept than in many other languages. This point is very

important for effective modeling in Python, and even more so for synthesizable MyHDL code.

Therefore, the issues are discussed here explicitly.

Consider the following name assignments:

a = 4

a = ``a string''

a = False

In many languages, the meaning would be that an existing variable a gets a number of different

values. In Python, such a concept of a variable doesn’t exist. Instead, assignment merely creates

a new binding of a name to a certain object, that replaces any previous binding. So in the

example, the name a is bound a number of different objects in sequence.

The converter has to investigate name assignment and usage in MyHDL code, and to map names

to Verilog or VHDL objects. To achieve that, it tries to infer the type and possibly the bit width of

each expression that is assigned to a name.

Multiple assignments to the same name can be supported if it can be determined that a consistent

type and bit width is being used in the assignments. This can be done for boolean expressions,

numeric expressions, and enumeration type literals.

In other cases, a single assignment should be used when an object is created. Subsequent value

changes are then achieved by modification of an existing object. This technique should be used

for Signal and intbv objects.

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Signal assignment in MyHDL is implemented using attribute assignment to attribute next. Value

changes are thus modeled by modification of the existing object. The converter investigates the

Signal object to infer the type and bit width of the corresponding Verilog or VHDL object.

intbv(

Type intbv is likely to be the workhorse for synthesizable modeling in MyHDL. An intbv instance

behaves like a (mutable) integer whose individual bits can be accessed and modified. Also, it is

possible to constrain its set of values. In addition to error checking, this makes it possible to infer a

bit width, which is required for implementation.

As noted before, it is not possible to modify value of an intbv object using name assignment. In

the following, we will show how it can be done instead. Consider:

a = intbv(0)[8:]

This is an intbv object with initial value 0 and bit width 8. To change its value to 5, we can use

slice assignment:

a[8:] = 5

The same can be achieved by leaving the bit width unspecified, which has the meaning to change

“all” bits:

a[:] = 5

Often the new value will depend on the old one. For example, to increment an intbv with the

technique above:

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