Microchip DSP33EP芯片硅错误勘误与数据表更新

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本文档是针对Microchip Technology Inc.的dspic33ep系列芯片（包括dsPIC33EPXXXGP50X、dsPIC33EPXXXMC20X/50X和PIC24EPXXXGP/MC20X）的一项勘误表，发布于2011年至2013年期间。这些芯片在功能上符合当时的Device Data Sheet（DS70000657H），但存在一些异常情况，这些异常被记录在这份文档中。问题主要涉及芯片的硅片版本，具体问题列表见表1，硅片修订问题在表2中进行了总结。文中指出，文中描述的错误将在未来对dsPIC33EPXXXGP50X、dsPIC33EPXXXMC20X/50X和PIC24EPXXXGP/MC20X的硅片修订中得到解决。对于已接收的设备，用户可能需要关注这些硅片修订，以确保其性能和稳定性。对于数据表的澄清和修正，用户可以查阅从第23页开始的部分，这部分内容是在讨论硅片问题之后提供的。识别芯片的硅片修订级别可以通过使用Microchip的MPLAB® IDE、Microchip的程序员、调试器和仿真工具进行，这些工具可以从Microchip官方网站（www.microchip.com）获取。例如，通过MPLAB IDE配合MPLAB ICD3或PICkit™3，用户可以按照文档中的步骤来检查其使用的芯片的具体硅片版本。这份勘误表对于使用这些芯片的开发人员和工程师来说具有重要价值，因为它提供了关于潜在问题的及时更新，以及如何处理这些问题的方法，有助于确保项目的顺利进行和产品性能的可靠性。在实际应用中，开发者应确保他们的硬件版本与文档中的信息保持一致，并根据需要采取相应的补丁或升级措施。

 2011-2013 Microchip Technology Inc. DS80000533G-page 5

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

TABLE 2: SILICON ISSUE SUMMARY

Module Feature

Item

Number

Issue Summary

CPU div.sd 1. When using the div.sd instruction, the overflow bit is not getting set

when an overflow occurs.

CPU DO Loop 2. PSV access, including table reads or writes in the last instruction of a

DO loop is not allowed.

SPI Frame Sync Pulse 3. Frame Sync pulse is not generated in Master mode when FRMPOL

= 0.

SPI Frame Sync Pulse 4. When in SPI Slave mode, with the Frame Sync pulse set as an input,

FRMDLY must be set to ‘0’.

UART TX Interrupt 5. A Transmit (TX) interrupt may occur before the data transmission is

complete.

Power System Flash Regulator 6. The VREGSF (RCON<11>) bit always reads back as ‘0’.

ADC DONE bit 7. The ADC Conversion Status bit (DONE) does not work when an

external interrupt is selected as the ADC trigger source.

PTG Strobe Output 8. Strobe output pulse width is incorrectly dependent on the

PTGPWD<3:0> (PTGCON<7:4>) bit settings.

Op Amp Enabling Op Amp

mode

9. When using any of these Op Amp modules, or Analog Channels

AN0, AN3 or AN6, to sample external signals, bit

11 of the CMxCON

Op Amp AC/DC Electrical

Characteristics

10. The AC/DC electrical characteristics for the Op Amp module (and

the related ADC specifications) are not within the specifications

published in the current data sheet.

PWM Dead-Time

Compensation

11. Dead-Time Compensation is not enabled for Center-Aligned PWM

mode.

Flash Flash Programming 12. The stall mechanism may not function properly when erasing or

programming Flash memory.

QEI Index Counter 13. The QEI Index Counter does not count correctly in Quadrature

Detector mode.

QEI Modulo Mode 14. Modulo mode functionality is incorrect when the Count Polarity bit is

set.

PWM Master Time Base

Mode

15. In Master Time Base mode, writing to the period register, and any

other timing parameter of the PWM module, will cause the update of

the other timing parameter to take effect one PWM cycle after the

period update is effective.

ADC 1.1 Msps Sampling 16. Selecting the same ANx input (AN0 or AN3) for CH0 and CH1 to

achieve a 1.1 Msps sampling rate results in erroneous readings for

CH1.

ADC Channel Scan 17. Channel scanning is limited to AN0 through AN15.

Output Compare Interrupt 18. Under certain circumstances, an output compare match may cause

the Output Compare Interrupt Flag (OCxIF) bit to become set prior to

the Change-of-State (COS) of the OCx pin.

ECAN™ DMA 19. Write collisions on a DMA-enabled ECAN™ module do not generate

DMAC error traps.

PWM Immediate Update 20. Dead time is not asserted when PDCx is updated to cause an

immediate transition on the PWMxH and PWMxL outputs.

PWM Center-Aligned

Mode

21. PWMxH is asserted for 100% of the PWM period in Complementary

mode under certain circumstances.

PWM Complementary

Mode

22. With dead time greater than zero, 0% and 100% duty cycle cannot

be obtained on PWMxL and PWMxH outputs.

CPU Program Memory 23. Address error trap may occur while accessing certain program

memory locations.

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