TI AM335x Sitara 处理器用户手册：高性能特性详解

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"TI公司的AM335x Sitara™处理器是高性能的微处理器，主要应用于嵌入式设计。该处理器系列包括AM3359、AM3358、AM3357、AM3356、AM3354和AM3352等型号，适用于广泛的工业和消费类电子产品。用户手册详细介绍了这些处理器的特性和功能，为开发者提供了全面的技术指导。" TI公司的AM335x Sitara™处理器集成了多种先进特性，以满足高效能计算和低功耗的需求。其中，它搭载了一个最高可达1GHz的ARM Cortex-A8 32位RISC核心，能够执行复杂的计算任务。处理器还配备了8KB指令RAM和8KB数据RAM，两者均带有单位检错（奇偶校验）功能，确保了数据的可靠性和系统的稳定性。为了增强处理能力，AM335x还包括一个NEON SIMD协处理器，能提升多媒体和浮点运算的性能。此外，处理器内置了单周期32位乘法器，拥有64位累加器，支持高效的数学运算。它还配备有32KB L1指令缓存和32KB带有ECC的L1数据缓存，以及256KB L2缓存，以减少内存访问延迟，提高整体系统响应速度。 AM335x处理器的外围模块丰富多样，如增强型GPIO（General-Purpose Input/Output）模块，可以支持外部信号的移入/移出操作，并具有并行锁断功能。此外，还有中断控制器模块，能够处理多达128个中断请求，确保实时系统响应。处理器内建JTAG接口，便于进行仿真和调试工作。 TI的AM335x处理器还包含PRU-ICSS（Programmable Real-Time Unit Industrial Communication Subsystem），这是一个高度灵活的硬件子系统，用于处理系统输入事件。PRU-ICSS包含了两个独立的PRU（Programmable Real-Time Units），每个都有120字节的寄存器组，以及64KB专用RAM。PRU-ICSS还包括通用异步收发器（UART）、增强型捕捉模块（eCAP）、两个MII以太网端口（支持工业以太网协议如EtherCAT）、MDIO端口、通用片上存储器控制器（OCMC）以及外部存储器接口（EMIF）。 EMIF接口支持多种类型的外部存储器，如mDDR、DDR2、DDR3和DDR3L，其中mDDR最高支持200MHz时钟频率。PRCM模块则负责电源、复位和时钟管理，确保处理器在待机模式、深度休眠模式之间的平滑转换，同时优化功耗。 TI的AM335x Sitara™处理器是一款综合性的嵌入式处理器，结合了高性能CPU、丰富的I/O接口、高效的存储管理和强大的实时处理能力，是开发各种嵌入式应用的理想选择。用户手册详细阐述了这些特性和配置方法，为开发者提供了宝贵的参考资料。

Middle
Pin map section location
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
ZHCS488H –OCTOBER 2011 –REVISED MAY 2015
www.ti.com.cn
ZCZ Pin Map [Section Middle - Top View]
G H J K L M
18 MMC0_CMD RMII1_REF_CLK MII1_TXD3 MII1_TX_CLK MII1_RX_CLK MDC
17 MMC0_CLK MII1_CRS MII1_RX_DV MII1_TXD0 MII1_RXD3 MDIO
16 MMC0_DAT0 MII1_COL MII1_TX_EN MII1_TXD1 MII1_RXD2 MII1_RXD0
15 MMC0_DAT1 VDDS_PLL_MPU MII1_RX_ER MII1_TXD2 MII1_RXD1 USB0_CE
14 VDDSHV6 VDDSHV4 VDDSHV4 VDDSHV5 VDDSHV5 VSSA_USB
13 VDD_MPU VDD_MPU VDD_MPU VDDS VSS VDD_CORE
12 VSS VSS VDD_CORE VDD_CORE VSS VSS
11 VSS VDD_CORE VSS VSS VSS VDD_CORE
10 VDD_CORE VSS VSS VSS VSS VSS
9 VSS VSS VSS VSS VDD_CORE VSS
8 VSS VSS VSS VDD_CORE VDD_CORE VSS
7 VDD_CORE VSS VSS VSS VDD_CORE VSS
6 VDD_CORE VSS VSS VDD_CORE VDD_CORE VSS
5 VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VPP
4 DDR_RASn DDR_A14 DDR_VREF DDR_D12 DDR_D14 DDR_D1
3 DDR_CKE DDR_A13 DDR_VTP DDR_D11 DDR_D13 DDR_D0
2 DDR_RESETn DDR_CSn0 DDR_DQM1 DDR_D10 DDR_DQSn1 DDR_DQM0
1 DDR_ODT DDR_A1 DDR_D8 DDR_D9 DDR_DQS1 DDR_D15
16 Terminal Configuration and Functions Copyright © 2011–2015, Texas Instruments Incorporated
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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352

ZHCS488H –OCTOBER 2011 –REVISED MAY 2015

www.ti.com.cn

4.2 Pin Attributes

The AM335x Sitara Processors Technical Reference Manual (SPRUH73) and this document may

reference internal signal names when discussing peripheral input and output signals since many of the

AM335x package terminals can be multiplexed to one of several peripheral signals. The following table

has a Pin Name column that lists all device terminal names and a Signal Name column that lists all

internal signal names multiplexed to each terminal which provides a cross reference of internal signal

names to terminal names. This table also identifies other important terminal characteristics.

1. BALL NUMBER: Package ball numbers associated with each signals.

2. PIN NAME: The name of the package pin or terminal.

Note: The table does not take into account subsystem terminal multiplexing options.

3. SIGNAL NAME: The signal name for that pin in the mode being used.

4. MODE: Multiplexing mode number.

(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the

terminal corresponds to the name of the terminal. There is always a function mapped on the

primary mode. Notice that primary mode is not necessarily the default mode.

Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE

column.

(b) Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are

effectively used for alternate functions, while some modes are not used and do not correspond to a

functional configuration.

5. TYPE: Signal direction

– I = Input

– O = Output

– I/O = Input and Output

– D = Open drain

– DS = Differential

– A = Analog

– PWR = Power

– GND = Ground

Note: In the safe_mode, the buffer is configured in high-impedance.

6. BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low.

– 0: The buffer drives V

(pulldown or pullup resistor not activated)

0(PD): The buffer drives V

with an active pulldown resistor

– 1: The buffer drives V

(pulldown or pullup resistor not activated)

1(PU): The buffer drives V

with an active pullup resistor

– Z: High-impedance

– L: High-impedance with an active pulldown resistor

– H : High-impedance with an active pullup resistor

7. BALL RESET REL. STATE: State of the terminal after the active low PWRONRSTn terminal

transitions from low to high.

– 0: The buffer drives V

(pulldown or pullup resistor not activated)

0(PD): The buffer drives V

with an active pulldown resistor

– 1: The buffer drives V

(pulldown or pullup resistor not activated)

1(PU): The buffer drives V

with an active pullup resistor

– Z: High-impedance.

– L: High-impedance with an active pulldown resistor

– H : High-impedance with an active pullup resistor

8. RESET REL. MODE: The mode is automatically configured after the active low PWRONRSTn terminal

transitions from low to high.

9. POWER: The voltage supply that powers the terminal’s IO buffers.

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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352

ZHCS488H –OCTOBER 2011 –REVISED MAY 2015

www.ti.com.cn

Table 4-1. Pin Attributes (ZCE and ZCZ Packages)

BALL RESET BUFFER PULLUP

ZCE BALL ZCZ BALL TYPE BALL RESET RESET REL. ZCE POWER / HYS

PIN NAME [2] SIGNAL NAME [3] MODE [4] REL. STATE STRENGTH /DOWN TYPE I/O CELL [13]

NUMBER [1] NUMBER [1] [5] STATE [6] MODE [8] ZCZ POWER [9] [10]

[7] (mA) [11] [12]

B8 B6 AIN0 AIN0 0 A

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