Xilinx 7系列FPGA SelectIO资源用户指南翻译

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"UG471-7Series-SelectIO的全文翻译.docx 是一份关于Xilinx 7系列FPGA的SelectIO资源用户指南，详细介绍了该系列芯片的选择和使用相关知识。文档版本为V1.10，发布日期为2018年5月8日。" 7系列FPGA的SelectIO资源是Xilinx公司提供的专用输入/输出(I/O)接口技术，用于在FPGA与外部设备之间进行高效的数据传输。这份用户指南提供了关于如何选择和配置这些I/O资源的详细信息。 1. **SelectIO概述** SelectIO是Xilinx 7系列FPGA的一个核心特性，它支持多种I/O标准和速度等级，以适应广泛的系统需求。这些标准包括LVCMOS、LVTTL、HSTL、SSTL等，以及高速串行协议如PCIe、DDR3和GTL+等。通过灵活的I/O配置，用户可以根据具体应用选择最适合的I/O标准。 2. **SelectIO架构** SelectIO架构由多个组件组成，包括I/O缓冲器、电压转换器、时钟管理单元和数据对齐逻辑。这些组件协同工作，确保数据在FPGA内部和外部设备之间的准确传输，并能处理时钟域转换、数据宽度匹配等问题。 3. **I/O配置** 用户可以通过Xilinx的Vivado设计套件进行SelectIO的配置。这包括选择I/O标准、设置I/O速度、配置电压摆幅和电流驱动能力，以及定义I/O方向（输入、输出或双向）。配置过程中还需要考虑电源规划、信号完整性、电磁干扰（EMI）等因素。 4. **I/O性能优化** 为了达到最佳性能，用户需要了解并考虑各种因素，如信号质量、电源稳定性、走线长度和阻抗匹配。Xilinx的用户指南会提供指导，帮助用户在设计中进行这些关键参数的优化。 5. **时钟管理和同步** SelectIO支持多时钟域操作，这意味着在一个系统中可以有多个不同的时钟源。时钟管理单元负责确保数据在不同时钟域之间正确同步，防止数据丢失或错误。 6. **错误检测和保护** 为了提高系统的可靠性，SelectIO可能包含错误检测和纠正机制，如奇偶校验、CRC校验等，以检测和修复数据传输过程中的错误。 7. **电源管理和功耗** SelectIO资源的设计考虑到低功耗要求，用户可以配置I/O电源以满足不同应用场景的功耗限制。 8. **兼容性和互操作性** Xilinx 7系列FPGA的SelectIO设计兼容多种标准，可以与各种外部设备无缝连接，如微处理器、存储器和其他FPGA或ASIC。 9. **故障排除和调试** 用户指南会提供故障排查步骤和建议，帮助用户诊断和解决SelectIO相关的问题，包括信号质量问题、时序违规等。 UG471是理解并有效利用Xilinx 7系列FPGA SelectIO功能的关键参考资料，它涵盖了从基础概念到高级配置的所有方面，为设计人员提供了全面的指导。

ISERDESE2 Feedback from OSERDESE2............................................................................................................................156

来自OSERDESE2的ISERDESE2反馈 .....................................................................156

Using D and DDLY in the ISERDESE2................................................................................................................................157

在ISERDESE2中使用d和ddly .........................................................................157

ISERDESE2 Timing Model and Parameters .......................................................................................................................157

ISERDESE2定时模型及参数 ..........................................................................157

Timing Characteristics............................................................................................................................................................................157

定时特性 ..................................................................................................157

ISERDESE2 VHDL and Verilog Instantiation Template...................................................................................................158

ISERDESE2 VHDL和Verilog实例化模板 ................................................................158

BITSLIP Submodule ...............................................................................................................................................................158

位滑子模块 .......................................................................................158

Bitslip Operation .....................................................................................................................................................................................158

位滑运算 ..................................................................................................158

Bitslip Timing Model and Parameters .................................................................................................................................................160

位滑定时模型及参数 ........................................................................................160

Output Parallel-to-Serial Logic Resources (OSERDESE2) .....................................................................161

输出并行到串行逻辑资源(OSERDESE2) ....................................................161

Data Parallel-to-Serial Converter..........................................................................................................................................................161

数据并串转换器 ............................................................................................161

3-State Parallel-to-Serial Conversion....................................................................................................................................................162

三态并串转换 ..............................................................................................162

OSERDESE2 Primitive ...........................................................................................................................................................162

Oserdese2原语 ....................................................................................162

OSERDESE2 Ports...................................................................................................................................................................163

OSERDESE2端口 ....................................................................................163

Data Path Output - OQ...........................................................................................................................................................................163

数据路径输出-OQ ...........................................................................................163

Output Feedback from OSERDESE2 - OFB.........................................................................................................................................163

来自OSERDESE2-OFB的输出反馈 ...............................................................................163

3-state Control Output - TQ...................................................................................................................................................................164

3状态控制输出-TQ ..........................................................................................164

3-state Control Output - TFB .................................................................................................................................................................164

三态控制输出-TFB ..........................................................................................164

High-Speed Clock Input - CLK.............................................................................................................................................................164

高速时钟输入-CLK ..........................................................................................164

Divided Clock Input - CLKDIV ............................................................................................................................................................164

分频时钟输入-CLKDIV .......................................................................................164

Parallel Data Inputs - D1 to D8..............................................................................................................................................................164

并行数据输入-D1至D8 .......................................................................................164

Reset Input - RST.....................................................................................................................................................................................164

复位输入-RST ..............................................................................................164

Output Data Clock Enable - OCE .........................................................................................................................................................164

输出数据时钟使能-OCE ......................................................................................164

3-state Signal Clock Enable - TCE.........................................................................................................................................................164

3状态信号时钟使能-TCE .....................................................................................164

Parallel 3-state Inputs - T1 to T4............................................................................................................................................................164

并行3态输入--T1至T4 .......................................................................................164

OSERDESE2 Attributes..........................................................................................................................................................165

OSERDESE2属性 ....................................................................................165

DATA_RATE_OQ Attribute..................................................................................................................................................................165

data_rate_oq属性 ..........................................................................................165

DATA_RATE_TQ Attribute ..................................................................................................................................................................165

data_rate_tq属性 ..........................................................................................165

DATA_WIDTH Attribute ......................................................................................................................................................................166

data_width属性 ............................................................................................166

SERDES_MODE Attribute .....................................................................................................................................................................166

SERDES_MODE属性 ...........................................................................................166

TRISTATE_WIDTH Attribute ...............................................................................................................................................................166

tristate_width属性 ........................................................................................166

OSERDESE2 Clocking Methods ...........................................................................................................................................166

Oserdese2时钟方法 ................................................................................166

OSERDESE2 Width Expansion.............................................................................................................................................167

Oserdese2宽度扩展 ................................................................................167

Guidelines for Expanding the Parallel-to-Serial Converter Bit Width............................................................................................168

扩展并串转换器位宽的指南 ..................................................................................168

Output Feedback ....................................................................................................................................................................168

输出反馈 .........................................................................................168

Send Feedback

发送反馈

OSERDESE2 Latencies ...........................................................................................................................................................168

OSERDESE2延迟 ....................................................................................168

DEFAULT Interface Type Latencies.....................................................................................................................................................168

默认接口类型延迟 ..........................................................................................168

OSERDESE2 Timing Model and Parameters......................................................................................................................169

OSERDESE2定时模型及参数 ..........................................................................169

Timing Characteristics of 2:1 SDR Serialization .................................................................................................................................170

2：1 SDR串行化的时序特性 ..................................................................................170

Timing Characteristics of 8:1 DDR Serialization ................................................................................................................................171

8：1 DDR串行化的时序特性 ..................................................................................171

Timing Characteristics of 4:1 DDR 3-State Controller Serialization ................................................................................................172

4：1 DDR三态控制器串行化的时序特性 ........................................................................172

OSERDESE2 VHDL and Verilog Instantiation Templates ...............................................................................................173

Oserdese2 VHDL和Verilog实例化模板 ................................................................173

IO_FIFO Overview .........................................................................................................................................173

IO_FIFO概述 ..........................................................................173

IN_FIFO....................................................................................................................................................................................174

IN_FIFO ..........................................................................................174

IN_FIFO Primitive...................................................................................................................................................................................175

IN_FIFO原语 ...............................................................................................175

OUT_FIFO ...............................................................................................................................................................................177

OUT_FIFO .........................................................................................177

OUT_FIFO Primitive...............................................................................................................................................................................178

OUT_FIFO原语 ..............................................................................................178

Resetting the IO_FIFO............................................................................................................................................................180

重置IO_FIFO ......................................................................................180

EMPTY and FULL Flags ........................................................................................................................................................180

空和满标志 .......................................................................................180

ALMOST EMPTY and ALMOST FULL Flags....................................................................................................................180

几乎空的和几乎满的旗帜 ...........................................................................180

Appendix A: Termination Options for SSO Noise Analysis

附录A：SSO噪声分析的终端选项

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 9

7系列FPGAS选择资源用户指南 www.xilinx.com 9

UG471 (v1.10) May 8, 2018

UG471(V1.10)2018年5月8日

Preface

前言

About This Guide

关于本指南

Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to enable a common design to

scale across families for optimal power, performance, and cost. The Spartan®-7 family is the lowest density with the

lowest cost entry point into the 7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt

and bandwidth-per-watt for cost-sensitive, high volume applications. The Kintex®-7 family is an innovative class of

FPGAs optimized for the best price-performance. The Virtex®-7 family is optimized for highest system performance

and capacity.

Xilinx®7系列FPGA包括四个FPGA系列，均采用最低功耗设计，使通用设计能够跨系列扩展，以获得最佳功耗、性能和成

本。 Spartan®-7系列是7系列产品中密度最低、成本最低的产品。 Artix®-7系列针对成本敏感、大容量应用的最高每

瓦性能和每瓦带宽进行了优化。 KINTEX®-7系列是一种创新的FPGAs系列，为最佳性价比而优化。 Virtex®-7系列针对

最高的系统性能和容量进行了优化。

This guide serves as a technical reference describing the 7 series FPGAs SelectIO™ resources. This 7 series FPGAs

SelectIO resources user guide, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx

website at www.xilinx.com/documentation.

本指南作为描述7系列FPGAS Selectio™资源的技术参考资料。 7系列FPGAs Selectio Resources用户指南是关于7系列

FPGAs的完整文档集的一部分，可在Xilinx网站上获得 www.xilinx.com/documentation .

Guide Contents

指南内容

This manual contains the following chapters:

本手册包含以下章节：

•

Chapter 1, SelectIO Resources

第1章，选择资源

•

Chapter 2, SelectIO Logic Resources

第二章，选择逻辑资源

•

Chapter 3, Advanced SelectIO Logic Resources

第3章，高级选择逻辑资源

Additional Resources

额外资源

To find additional documentation, see the Xilinx website at: http://www.xilinx.com/support/documentation/index.htm.

要找到其他文档，请参阅Xilinx网站： http://www.xilinx.com/support/documentation/index.htm .

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support

WebCase, see the Xilinx website at:

要搜索Silicon、Software和IP问题和答案的答案数据库，或创建技术支持WebCase，请参见Xilinx网站：

http://www.xilinx.com/support.

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