TI-DLP5531-Q1: 0.55英寸1.3百万像素DMD，专为汽车外饰照明设计

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TI-DLP5531-Q1是一款专为汽车外饰照明设计的0.55英寸1.3百万像素数字微镜(DMD)。这款产品在汽车行业中具有重要地位，因为它具备了严格的工业级性能，特别是在极端温度条件下（-40°C至105°C），确保了在严苛环境中的稳定运行。其主要特性包括： 1. **专为汽车应用设计**：该DMD模块经过认证，适用于汽车系统，能够在宽广的工作温度范围内提供可靠的性能。 2. **高分辨率显示**：1.3百万像素的分辨率使得它能实现清晰、细腻的图像投影，适用于各种复杂的照明需求，如车灯、仪表盘照明等。 3. **电源管理与控制**：支持VBATT、Flash和TPS99000-Q1电源序列和监控功能，确保不同电压供电的精确管理和稳定性。此外，还有MPU（微处理器）进行电源调节和监控，以及I2C接口用于连接外部监控设备。 4. **图像处理能力**：内置DLPC230-Q1和eSRAM作为帧缓冲器，能够进行高效的图像处理和存储，实现灵活的图像缩放。 5. **LED驱动**：具备专为LED照明设计的驱动电路，能够有效控制LED的亮度和颜色。 6. **多接口支持**：包括SPI、I2C通信接口，方便与外部控制器和传感器连接，以及GPIO配置选项，提高系统的灵活性。 7. **光照控制与反馈**：内置光照控制模块，允许用户根据环境调整照明效果，并通过photodiode进行反馈，实现动态调整。 8. **状态指示与信号同步**：提供6.5V的电压等级，以及24-bit RGB同步信号，便于外部设备了解工作状态。 9. **保护机制**：内置重置和电源好的信号，以及OpenLDI功能，确保系统的安全性和可靠性。 10. **版权和法律声明**：文档最后的注意事项强调了产品的可用性、保修信息、在安全关键应用中的使用限制、知识产权声明以及生产数据更新。 TI-DLP5531-Q1是一款高性能、低功耗的DMD解决方案，为汽车行业提供了卓越的照明控制能力和适应各种严苛环境的能力，是现代汽车照明系统设计不可或缺的关键组件。

DLP5531-Q1

DLPS075G –APRIL 2016–REVISED MAY 2019

www.ti.com

Product Folder Links: DLP5531-Q1

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:

VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.

(3) VOFFSET supply transients must fall within specified voltages.

(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current

draw.

(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.

(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential

inputs must not exceed the specified limit or damage to the internal termination resistors may result.

(8) See Micromirror Array Temperature Calculation section.

6 Specifications

6.1 Absolute Maximum Ratings

see

(1)

MIN MAX UNIT

SUPPLY VOLTAGE

VDD

Supply voltage for LVCMOS core logic

(2)

Supply voltage for LPSDR low speed interface

–0.5 2.3 V

VDDI Supply voltage for SubLVDS receivers

(2)

–0.5 2.3 V

VOFFSET Supply voltage for HVCMOS and micromirror electrode

(2)(3)

–0.5 8.75 V

VBIAS Supply voltage for micromirror electrode

(2)

–0.5 17 V

VRESET Supply voltage for micromirror electrode

(2)

–11 0.5 V

| VDDI–VDD | Supply voltage delta (absolute value)

(4)

0.3 V

| VBIAS–VOFFSET | Supply voltage delta (absolute value)

(5)

8.75 V

| VBIAS–VRESET | Supply voltage delta (absolute value)

(6)

28 V

INPUT VOLTAGE

Input voltage for other inputs LPSDR

(2)

–0.5 VDD + 0.5 V

Input voltage for other inputs SubLVDS

(2)(7)

–0.5 VDDI + 0.5 V

INPUT PINS

| V

| SubLVDS input differential voltage (absolute value)

(7)

810 mV

SubLVDS input differential current 10 mA

CLOCK FREQUENCY

clock

Clock frequency for low speed interface LS_CLK 130 MHz

clock

Clock frequency for high speed interface DCLK 620 MHz

ENVIRONMENTAL

ARRAY

Operating DMD array temperature

(Monitored by TMP411 via DLPC230-Q1)

(8)

–40 105 °C

6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system.

MIN MAX UNIT

stg

DMD storage temperature (Reference location TP1 in Figure 19) –40 125 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic

discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

±2000

VCharged-device model (CDM), Corner Pins, per JESD22-C101

(2)

±750

Charged-device model (CDM), All Other Pins, per JESD22-C101

(2)

±500

DLP5531-Q1

www.ti.com

DLPS075G –APRIL 2016–REVISED MAY 2019

Product Folder Links: DLP5531-Q1

(1) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections

are also required.

(2) Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(3) All voltage values are with respect to the ground pins (VSS).

(4) VOFFSET supply transients must fall within specified max voltages.

(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.

(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.

(7) Refer to the SubLVDS timing requirements in Timing Requirements.

(8) Temperature Diode is to allow accurate measurement of the DMD array temperature during operation.

(9) DMD Active Array temperature can be calculated using the TMP411 and DLPC230-Q1 as shown in the Micromirror Array Temperature

Calculation section.

(10) The maximum operation conditions for operating temperature and UV illumination shall not be implemented simultaneously.

(11) Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested.

(12) The active area of the DLP5531-Q1 device is surrounded by an aperture on the inside of the DMD window surface that masks

structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light

illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the

DMD. The illumination optical system should be designed to minimize light flux incident outside the active array. Depending on the

particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause

system performance degradation.

(13) Applies to the two regions in Figure 1.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

(1)(2)

MIN NOM MAX UNIT

SUPPLY VOLTAGE RANGE

(3)

VDD

Supply voltage for LVCMOS core logic

Supply voltage for LPSDR low-speed interface

1.7 1.8 1.95 V

VDDI Supply voltage for SubLVDS receivers 1.7 1.8 1.95 V

VOFFSET Supply voltage for HVCMOS and micromirror electrode

(4)

8.25 8.5 8.75 V

VBIAS Supply voltage for mirror electrode 15.5 16 16.5 V

VRESET Supply voltage for micromirror electrode –9.5 –10 –10.5 V

| VDDI–VDD | Supply voltage delta (absolute value)

(5)

0.3 V

| VBIAS–VOFFSET | Supply voltage delta (absolute value)

(6)

8.75 V

CLOCK FREQUENCY

clock

Clock frequency for low speed interface LS_CLK 120 MHz

clock

Clock frequency for high speed interface DCLK

(7)

600 MHz

Duty cycle distortion DCLK 44% 56%

SUBLVDS INTERFACE

(7)

| V

SubLVDS input differential voltage (absolute value,

see Figure 6, Figure 7)

150 250 350 mV

Common mode voltage (see Figure 6, Figure 7) 700 900 1100 mV

SUBLVDS

SubLVDS voltage (see Figure 6, Figure 7) 575 1225 mV

LINE

Line differential impedance (PWB/trace) 90 100 110 Ω

Internal differential termination resistance (see Figure 8) 80 100 120 Ω

TEMPERATURE DIODE

TEMP_DIODE

Max current source into Temperature Diode

(8)

120 µA

ENVIRONMENTAL

ARRAY

Operating DMD array temperature

(9)(10)(11)

–40 105 °C

ILL

Illumination, wavelength < 395 nm

(10)

2 mW/cm

ILL

OVERFILL

Illumination overfill maximum

heat load per side.

(12)(13)

ARRAY

<= 75°C 40 mW/mm

ILL

OVERFILL

Illumination overfill maximum

heat load per side.

(12)(13)

ARRAY

> 75°C 29 mW/mm

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TI-DLP5531-Q1: 0.55英寸1.3百万像素DMD，专为汽车外饰照明设计

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