Xilinx Spartan-3E XC3S500E-4FGG320C 数据手册概览

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"XC3S500E-4FGG320C是Xilinx公司的一款FPGA（Field-Programmable Gate Array）芯片的详细数据手册，包含了该芯片的全面技术规格和功能描述。" 在《XC3S500E-4FGG320C datasheet》中，我们能了解到以下几个主要的知识点： 1. **模块1：介绍与订购信息** - **简介**：这部分通常会概述XC3S500E-4FGG320C的基本特性，包括它的设计目标、应用领域以及在系统设计中的角色。 - **特性**：列出该器件的主要功能，比如其逻辑门数量、I/O口数量、功耗、速度等级等。 - **架构概览**：简述了XC3S500E-4FGG320C的内部结构，包括其基本组成单元。 - **封装标记**：提供封装信息，如引脚数、封装类型（4FGG320C代表的是4层扁平无引线封装，320个引脚）。 - **订购信息**：指导用户如何正确选择和订购该产品，可能包含不同的速度等级、温度范围等选项。 2. **模块2：功能描述** - **输入/输出块（IOBs）**：详细介绍了XC3S500E-4FGG320C的IOB，包括其灵活性和可配置性，以及SelectIO信号标准，用于支持不同的接口协议。 - **可配置逻辑块（CLB）**：CLB是FPGA的基本构建块，用于实现用户逻辑。 - **块RAM**：内嵌的存储器资源，可用于实现快速的随机存取存储功能。 - **专用乘法器**：FPGA内部集成的硬件乘法器，提高计算效率。 - **数字时钟管理器（DCM）**：提供时钟频率合成、倍频、分频和相位调整等功能，以满足系统时钟需求。 - **时钟网络**：描述了芯片内的时钟分布和管理机制。 - **配置**：详细说明如何对FPGA进行编程和配置。 - **供电**：关于Spartan-3E FPGA系列的电源要求和推荐的电源方案。 3. **模块3：直流和开关特性** - **直流电气特性**：列出器件的绝对最大额定值、电源电压规格、推荐工作条件和直流特性，这些对于确保芯片安全运行至关重要。 - **开关特性**：包含配置和JTAG时序在内的高速信号操作的定时参数。 4. **模块4：引脚描述** - **引脚布局**：详尽地列出每个引脚的功能，帮助用户了解如何连接外部电路和理解板级设计。这份数据手册提供了设计者使用XC3S500E-4FGG320C进行系统开发所需的所有关键信息，包括硬件规格、功能特性和操作指南，对于理解和应用这款FPGA芯片来说是不可或缺的参考材料。

Functional Description

DS312-2 (v1.1) March 21, 2005 www.xilinx.com 9

Advance Product Specification

HSTL and SSTL inputs use the Reference Voltage (V

REF

) to

bias the input-switching threshold. Once a configuration

data file is loaded into the FPGA that calls for the I/Os of a

given bank to use HSTL/SSTL, a few specifically reserved

I/O pins on the same bank automatically convert to V

REF

inputs. For banks that do not contain HSTL or SSTL, V

REF

pins remain available for user I/Os or input pins.

Differential standards employ a pair of signals, one the

opposite polarity of the other. The noise canceling proper-

ties (for example, Common-Mode Rejection) of these stan-

dards permit exceptionally high data transfer rates. This

subsection introduces the differential signaling capabilities

of Spartan-3E devices.

Each device-package combination designates specific I/O

pairs specially optimized to support differential standards.

Differential pairs can be shown in the Pin and Area Con-

straints Editor (PACE) with the “Show Differential Pairs”

option. A unique

L-number

, part of the pin name, identifies

the line-pairs associated with each bank (see Module 4

For each pair, the letters

and

designate the true and

inverted lines, respectively. For example, the pin names

IO_L43P_3 and IO_L43N_3 indicate the true and inverted

lines comprising the line pair L43 on Bank 3.

CCO

provides current to the outputs and additionally pow-

ers the On-Chip Differential Termination. V

CCO

must be

2.5V when using the On-Chip Differential Termination. The

REF

lines are not required for differential operation.

To further understand how to combine multiple IOSTAN-

DARDs within a bank, refer to IOBs Organized into Banks,

page 10.

On-Chip Differential Termination

Spartan-3E devices provide an on-chip 100Ω differential

termination across the input differential receiver terminals

(See Module 3

for the specific range). The on-chip input dif-

ferential termination in Spartan-3E devices eliminates the

external 100Ω termination resistor commonly found in dif-

ferential receiver circuits. Use differential termination for

LVDS, mini-LVDS, and BLVDS as applications permit.

On-chip Differential Termination is available in banks with

CCO

= 2.5V and is not supported on dedicated input pins.

Set the DIFF_TERM attribute to TRUE to enable Differential

Termination on a differential I/O pin pair.

The DIFF_TERM attribute uses the following syntax in the

UCF file:

INST <I/O_BUFFER_INSTANTIATION_NAME>

DIFF_TERM = “<TRUE/FALSE>”;

Pull-Up and Pull-Down Resistors

Pull-up and pull-down resistors inside each IOB optionally

force a floating I/O pin to a determined state. Pull-up and

Table 4:

Differential IOSTANDARD Bank Compatibility

Differential

IOSTANDARD

CCO

Supply

Input Requirements: V

REF

2.5V 3.3V

LVDS_25

Input,

On-chip Differential Termination,

Output

(1)

Input

N/R

(Not Required)

RSDS_25

Input,

On-chip Differential Termination,

Output

(1)

Input

MINI_LVDS_25

Input,

On-chip Differential Termination,

Output

(1)

Input

LVPECL_25

Input,

On-chip Differential Termination

Input

BLVDS_25

Input,

On-chip Differential Termination,

Output

Input

Notes:

1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.

Figure 8:

Differential Inputs and Outputs

100Ω

Spartan-3E

Differential Input

= 50Ω

Spartan-3E

Differential

Output

Spartan-3E

Differential Input

with On-Chip

Differential

Terminator

= 50Ω

Spartan-3E

Differential

Output

DS312-2_24_021505

Functional Description

10 www.xilinx.com DS312-2 (v1.1) March 21, 2005

Advance Product Specification

pull-down resistors are commonly applied to unused I/Os,

inputs, and three-state outputs, but can be used on any I/O.

The pull-up resistor connects an I/O to V

CCO

through a

resistor. The resistance value depends on the V

CCO

voltage

(see Module 3

for the specifications). The pull-down resistor

similarly connects an I/O to ground with a resistor. The PUL-

LUP and PULLDOWN attributes and library primitives turn

on these optional resistors.

By default, PULLDOWN resistors terminate all unused I/Os.

Unused I/Os can alternatively be set to PULLUP or FLOAT.

To change the unused I/O Pad setting, set the Bitstream

Generator (BitGen) option

UnusedPin

to PULLUP, PULL-

DOWN, or FLOAT. The

UnusedPin

option is accessed

through the Properties for Generate Programming File in

ISE.

During configuration a Low logic level on HSWAP activates

the pull-up resistors for all I/Os not used directly in the

selected configuration mode.

Keeper Circuit

Each I/O has an optional keeper circuit (see Figure 9) that

keeps bus lines from floating when not being actively driven.

The KEEPER circuit retains the last logic level on a line after

all drivers have been turned off. Apply the KEEPER

attribute or use the KEEPER library primitive to use the

KEEPER circuitry. Pull-up and pull-down resistors override

the KEEPER settings.

Slew Rate Control and Drive Strength

Each IOB has a slew-rate control that sets the output

switching edge-rate for LVCMOS and LVTTL outputs. The

SLEW attribute controls the slew rate and can either be set

to SLOW (default) or FAST.

Each LVCMOS and LVTTL output additionally supports up

to six different drive current strengths as shown in Ta bl e 5.

To adjust the drive strength for each output set the DRIVE

attribute to the desired drive strength: 2, 4, 6, 8, 12, and 16.

High output current drive strength and FAST output slew

rates generally result in fastest I/O performance. However,

these same settings generally also result in transmission

line effects on the printed circuit board (PCB) for all but the

shortest board traces. Each IOB has independent slew rate

and drive strength controls. Use the slowest slew rate and

lowest output drive current that meets the performance

requirements for the end application.

Likewise, due to lead inductance, a given package supports

a limited number of simultaneous switching outputs (SSOs)

when using fast, high-drive outputs. Only use fast,

high-drive outputs when required by the application.

IOBs Organized into Banks

The Spartan-3E architecture organizes IOBs into four I/O

banks as shown in Figure 10. Each bank maintains sepa-

rate V

CCO

and V

REF

supplies. The separate supplies allow

each bank to independently set V

CCO

. Similarly, the V

REF

supplies may be set for each bank. Refer to Table 3 and

Table 4 for V

CCO

and V

REF

requirements.

When working with Spartan-3E devices, most of the differ-

ential I/O standards are compatible and can be combined

within any given bank. Each bank can support any two of

the following differential standards: LVDS_25 outputs,

MINI_LVDS_25 outputs, and RSDS_25 outputs. As an

example, LVDS_25 outputs, RSDS_25 outputs, and any

other differential inputs while using on-chip differential ter-

mination are a valid combination. A combination not allowed

is a single bank with LVDS_25 outputs, RSDS_25 outputs,

and MINI_LVDS_25 outputs.

Figure 9:

Keeper Circuit

Weak Pull-up

Weak Pull-down

Input Path

Output Path

Keeper

DS312-2_25_022805

Table 5:

Programmable Output Drive Current

Signal

Standard

Output Drive Current (mA)

2 4 6 8 12 16

LVTTL



LVCMOS33 

LVCMOS25  -

LVCMOS18

 - -

LVCMOS15

 - - -

LVCMOS12

 - - - - -

Functional Description

DS312-2 (v1.1) March 21, 2005 www.xilinx.com 11

Advance Product Specification

I/O Banking Rules

When assigning I/Os to banks, these V

CCO

rules must be

followed:

1. All V

CCO

pins on the FPGA must be connected even if a

bank is unused.

2. All V

CCO

lines associated within a bank must be set to

the same voltage level.

3. The V

CCO

levels used by all standards assigned to the

I/Os of any given bank must agree. The Xilinx

development software checks for this. Table 3 and

Table 4 describe how different standards use the V

CCO

supply.

4. If a bank does not have any V

CCO

requirements,

connect V

CCO

to an available voltage, such as 2.5V or

3.3V. Some configuration modes might place additional

CCO

requirements. Refer to Configuration, page 56

for more information.

If any of the standards assigned to the Inputs of the bank

use V

REF

, then the following additional rules must be

observed:

1. All V

REF

pins must be connected within a bank.

2. All V

REF

lines associated with the bank must be set to

the same voltage level.

3. The V

REF

levels used by all standards assigned to the

Inputs of the bank must agree. The Xilinx development

software checks for this. Table 3 describes how different

standards use the V

REF

supply.

If V

REF

is not required to bias the input switching thresholds,

all associated V

REF

pins within the bank can be used as

user I/Os or input pins.

Package Footprint Compatibility

Sometimes, applications outgrow the logic capacity of a

specific Spartan-3E FPGA. Fortunately, the Spartan-3E

family is designed so that multiple part types are available in

pin-compatible package footprints, as described in Module

4. In some cases, there are subtle differences between

devices available in the same footprint. These differences

are outlined for each package, such as pins that are uncon-

nected on one device but connected on another in the same

package or pins that are dedicated inputs on one package

but full I/O on another. When designing the printed circuit

board (PCB), plan for potential future upgrades and pack-

age migration.

The Spartan-3E family is not pin-compatible with any previ-

ous Xilinx FPGA family.

Dedicated Inputs

Dedicated Inputs are IOBs used only as inputs. Pin names

designate a Dedicated Input if the name starts with

, for

example, IP or IP_Lxxx_x. Dedicated inputs retain the full

functionality of the IOB for input functions with a single

exception for differential inputs (IP_Lxxx_x). For the differ-

ential Dedicated Inputs, the on-chip differential termination

is not available. To replace the on-chip differential termina-

tion, choose a differential pair that supports outputs

(IO_Lxxx_x) or use an external 100Ω termination resistor on

the board.

ESD Protection

Clamp diodes protect all device pads against damage from

Electro-Static Discharge (ESD) as well as excessive voltage

transients. Each I/O has two clamp diodes: one diode

extends P-to-N from the pad to V

CCO

and a second diode

extends N-to-P from the pad to GND. During operation,

these diodes are normally biased in the off state. These

clamp diodes are always connected to the pad, regardless

of the signal standard selected. The presence of diodes lim-

its the ability of Spartan-3E I/Os to tolerate high signal volt-

ages. The V

absolute maximum rating in Table 1 of

Module 3

specifies the voltage range that I/Os can tolerate.

Supply Voltages for the IOBs

The IOBs are powered by three supplies:

1. The V

CCO

supplies, one for each of the FPGA’s I/O

banks, power the output drivers. The voltage on the

CCO

pins determines the voltage swing of the output

signal.

2. V

CCINT

is the main power supply for the FPGA’s internal

logic.

3. V

CCAUX

is an auxiliary source of power, primarily to

optimize the performance of various FPGA functions

such as I/O switching.

The I/Os During Power-On, Configuration, and

User Mode

All I/Os have ESD clamp diodes to their respective V

CCO

supply and from GND, as shown in Figure 1. The V

CCINT

(1.2V), V

CCAUX

(2.5V), and V

CCO

supplies can be applied in

any order. Before the FPGA can start its configuration pro-

cess, V

CCINT

, V

CCO

Bank 2, and V

CCAUX

must have

reached their respective minimum recommended operating

Figure 10:

Spartan-3E I/O Banks (top view)

DS312-2_26_021205

Bank 0

Bank 2

Bank 3

Bank 1

Functional Description

12 www.xilinx.com DS312-2 (v1.1) March 21, 2005

Advance Product Specification

levels (see Table 2 of Module 3). At this time, all I/O drivers

are in a high-impedance state. V

CCO

Bank 2, V

CCINT

, and

CCAUX

serve as inputs to the internal Power-On Reset cir-

cuit (POR).

A Low level applied to the HSWAP input enables pull-up

resistors on User I/Os from power-on throughout configura-

tion. A High level on HSWAP disables the pull-up resistors,

allowing the I/Os to float. HSWAP contains a weak pull-up

and defaults to High if left floating. As soon as power is

applied, the FPGA begins initializing its configuration mem-

ory. At the same time, the FPGA internally asserts the Glo-

bal Set-Reset (GSR), which asynchronously resets all IOB

storage elements to a default Low state.

Upon the completion of initialization and the beginning of

configuration, INIT_B goes High, sampling the M0, M1, and

M2 inputs to determine the configuration mode. At this point

in time, the configuration data is loaded into the FPGA. The

I/O drivers remain in a high-impedance state (with or with-

out pull-up resistors, as determined by the HSWAP input)

throughout configuration.

At the end of configuration, the GSR net is released, placing

the IOB registers in a Low state by default, unless the

loaded design reverses the polarity of their respective SR

inputs.

The Global Three State (GTS) net is released during

Start-Up, marking the end of configuration and the begin-

ning of design operation in the User mode. After the GTS

net is released, all user I/Os go active while all unused I/Os

are weakly pulled down (PULLDOWN). The designer can

control how the unused I/Os are terminated after GTS is

released by setting the Bitstream Generator (BitGen) option

UnusedPin to PULLUP, PULLDOWN, or FLOAT.

One clock cycle later (default), the Global Write Enable

(GWE) net is released allowing the RAM and registers to

change states. Once in User mode, any pull-up resistors

enabled by HSWAP revert to the user settings and HSWAP

is available as a general-purpose I/O. For more information

on PULLUP and PULLDOWN, see Pull-Up and Pull-Down

Resistors.

JTAG Boundary-Scan Capability

All Spartan-3E IOBs support boundary-scan testing com-

patible with IEEE 1149.1/1532 standards. See JTAG Mode,

page 86 for more information on programming via JTAG.

Functional Description

DS312-2 (v1.1) March 21, 2005 www.xilinx.com 13

Advance Product Specification

Configurable Logic Block (CLB) and

Slice Resources

CLB Overview

The Configurable Logic Blocks (CLBs) constitute the main

logic resource for implementing synchronous as well as

combinatorial circuits. Each CLB contains four slices, and

each slice contains two Look-Up Tables (LUTs) to imple-

ment logic and two dedicated storage elements that can be

used as flip-flops or latches. The LUTs can be used as a

16x1 memory (RAM16) or as a 16-bit shift register (SRL16),

and additional multiplexers and carry logic simplify wide

logic and arithmetic functions. Most general-purpose logic

in a design is automatically mapped to the slice resources in

the CLBs. Each CLB is identical, and the Spartan-3E family

CLB structure is identical to that for the Spartan-3 family.

CLB Array

The CLBs are arranged in a regular array of rows and col-

umns as shown in Figure 11.

Each density varies by the number of rows and columns of

CLBs (see Table 6).

Slices

Each CLB comprises four interconnected slices, as shown

in Figure 13. These slices are grouped in pairs. Each pair is

organized as a column with an independent carry chain.

The left pair supports both logic and memory functions and

its slices are called SLICEM. The right pair supports logic

only and its slices are called SLICEL. Therefore half the

LUTs support both logic and memory (including both

RAM16 and SRL16 shift registers) while half support logic

only, and the two types alternate throughout the array col-

umns. The SLICEL reduces the size of the CLB and lowers

the cost of the device, and can also provide a performance

advantage over the SLICEM.

Figure 11:

CLB Locations

DS312-2_31_021205

Spartan-3E

FPGA

X0Y1 X1Y1

X0Y0 X1Y0

IOBs

CLB

Slice

X2Y1 X3Y1

X2Y0 X3Y0

X0Y3 X1Y3

X0Y2 X1Y2

X2Y3 X3Y3

X2Y2 X3Y2

Table 6:

Spartan-3E CLB Resources

Device

CLB

Rows

CLB

Columns

CLB

Total

(1)

Slices

LUTs /

Flip-Flops

Equivalent

Logic Cells

RAM16 /

SRL16

Distributed

RAM Bits

XC3S100E 22 16 240 960 1920 2160 960 15360

XC3S250E 34 26 612 2448 4896 5508 2448 39168

XC3S500E 46 34 1164 4656 9312 10476 4656 74496

XC3S1200E 60 46 2168 8672 17344 19512 8672 138752

XC3S1600E 76 58 3688 14752 29504 33192 14752 236032

Notes:

1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are

embedded in the array (see Module 1

, Figure 1).

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