Xilinx Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide

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"Virtex-4 RocketIO Multi-Gigabit Transceiver UserGuide" Virtex-4系列是Xilinx公司推出的一款高性能FPGA（Field-Programmable Gate Array）产品，其中的RocketIO模块是其关键特性之一，专门用于实现高速串行数据传输。RocketIO多吉比特收发器（Multi-Gigabit Transceivers，简称MGTs）设计用于在FPGA内部和外部设备之间提供高带宽连接，支持多种通信协议如PCIe、Gigabit Ethernet、Serial ATA等。本用户手册——"Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide"（UG076 v4.1，发布于2008年11月2日）详细介绍了如何在Virtex-4 FPGA中配置和使用RocketIO MGT。手册涵盖了以下关键知识点： 1. **RocketIO概述**：解释了RocketIO MGT的基本架构和工作原理，包括其物理层（PHY）和逻辑层（MAC或LLP）的功能，以及它们如何协同处理高速数据传输。 2. **设计流程**：详细阐述了从设计初期的概念到最终实现的完整流程，包括系统级设计、时序分析、功耗评估、IP集成、布局布线和时钟管理。 3. **协议支持**：RocketIO MGT可以支持多种协议，手册会列出每种协议的配置方法，包括如何设置相应的接口和参数以满足特定标准。 4. **硬件接口**：介绍如何与外部设备建立物理连接，包括差分信号线的布局指导，以及信号完整性、眼图分析和信号质量测试的相关内容。 5. **时钟管理和同步**：讨论了RocketIO MGT对时钟的需求，包括时钟源的选择、时钟树的构建，以及时钟抖动和相位噪声的影响。 6. **电源管理**：提供了关于电源分配网络的设计建议，以确保MGT的稳定运行，同时降低功耗。 7. **故障排查和调试**：提供了一系列工具和技巧，帮助用户诊断和解决在设计过程中遇到的问题，如信号完整性问题、时序违规等。 8. **软件工具支持**：详细介绍了Xilinx ISE Design Suite和其他相关软件工具如何支持RocketIO MGT的设计和验证。 9. **版本更新和变更历史**：手册中包含了版本变更记录，列出了每次更新的主要改进和修复，帮助用户了解最新版本带来的变化。请注意，由于Xilinx有权随时更改文档而无需提前通知，因此在实际应用中，用户应始终参考最新的文档版本，以确保获取最准确的信息和技术支持。此外，使用这些文档进行设计开发时，需遵守Xilinx的使用条款，未经许可，不得复制、分发或以任何形式发布文档内容。Xilinx对于因使用此文档而导致的任何损失或责任不承担责任，并且不承诺对文档中的错误进行修正，也不承担与技术支持或协助相关的任何责任。

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Figure 3-2: Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 3-3: RX Ring Buffer Half-Full Upon Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 3-4: RX Ring Buffer Overflow and Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 3-5: Fabric Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 3-6: PCS Bypass Byte Mapping, 8-Byte External Fabric Width . . . . . . . . . . . . . . 107

Figure 3-7: PCS Bypass Byte Mapping, 4-Byte External Fabric Width . . . . . . . . . . . . . . 107

Figure 3-8: 8B/10B Parallel-to-Serial Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 3-9: 4-Byte Serial Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 3-10: 10-Bit TX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 3-11: 10-Bit RX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 3-12: 8B/10B Comma Detection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 3-13: 6-Bit Alignment Mux Position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 3-14: SONET Alignment Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 3-15: SONET Alignment Sequence (4-Byte External Data Interface Width) . . . 119

Figure 3-16: SONET Alignment Sequence (2-Byte External Data Interface Width) . . . 120

Figure 3-17: Comma Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 3-18: RXSLIDE Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 3-19: Effects of CCCB_ARBITRATOR_DISABLE = TRUE. . . . . . . . . . . . . . . . . . 130

Figure 3-20: Daisy-Chained Transceiver CHBONDI/CHBONDO Buses . . . . . . . . . . . . 131

Figure 3-21: XC4VFX20/XC4VFX60 Device Implementation . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 3-22: Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 3-23: Digital Receiver Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 3-24: PCS RXCLK Generation, Buffered Mode (Green) . . . . . . . . . . . . . . . . . . . . 136

Chapter 4: PMA Analog Design Considerations

Figure 4-1: Differential Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 4-2: 3-Tap Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 4-3: Effect of 3-Tap Pre-Emphasis on a Pulse Signal . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 4-4: TX with Minimal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 4-5: RX after 36 Inches FR4 and Minimal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . 144

Figure 4-6: TX with Maximal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 4-7: RX after 36 Inches FR4 and Maximal Pre-Emphasis . . . . . . . . . . . . . . . . . . . . 146

Figure 4-8: AC Response of Continuous-Time Linear Receiver Equalizer. . . . . . . . . . . 148

Figure 4-9: OOB Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Chapter 5: Cyclic Redundancy Check (CRC)

Figure 5-1: 32-bit CRC Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 5-2: 64-Bit to 32-Bit Core Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 5-3: Max Data Rate Example (64-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 5-4: Max Data Rate Example (32-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 5-5: 16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example . . . . . . . . . 160

Figure 5-6: CRC Generation Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

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UG076 (v4.1) November 2, 2008

Chapter 6: Analog and Board Design Considerations

Figure 6-1: MGT Tile Power and Serial I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 6-2: Internal Receiver AC Coupling with External DC Coupling between

Transmitter and Receiver Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 6-3: Power Supply Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 6-4: Power Filtering Network for One MGT Tile . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 6-5: Layout for Power Filtering Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 6-6: Optimizing Filtering for an MGT Column. . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 6-7: Reference Clock Oscillator Interface (Up to 400 MHz) . . . . . . . . . . . . . . . . . 170

Figure 6-8: Reference Clock VCSO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 6-9: Transmit Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 6-10: Simplified Receive Termination Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 6-11: AC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 6-12: AC Coupling Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 6-13: DC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 6-14: Single-Ended Trace Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 6-15: Obstacle Route Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 6-16: Microstrip Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 6-17: Stripline Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Chapter 7: Simulation and Implementation

Chapter 8: Low-Latency Design

Figure 8-1: PCS Receive Clocking Domains and Data Paths. . . . . . . . . . . . . . . . . . . . . . . 192

Figure 8-2: PCS Transmit Clocking Domains and Data Paths . . . . . . . . . . . . . . . . . . . . . 193

Figure 8-3: Using GREFCLK as Synchronization Clock (Use Models TX_2A-H) . . . . . 200

Figure 8-4: TX Low Latency Buffered Mode: Use Models TX_1A, TX_2A . . . . . . . . . . . 202

Figure 8-5: TX Low Latency Buffered Mode: Use Models TX_1B, TX_2B. . . . . . . . . . . . 203

Figure 8-6: TX Low Latency Buffered Mode: Use Models TX_1C, TX_2C . . . . . . . . . . . 204

Figure 8-7: TX Low Latency Buffered Mode: Use Models TX_1D, TX_2D . . . . . . . . . . . 205

Figure 8-8: TX Low Latency Buffered Mode: Use Model TX_2E. . . . . . . . . . . . . . . . . . . . 206

Figure 8-9: TX Low Latency Buffered Mode: Use Model TX_2F. . . . . . . . . . . . . . . . . . . . 207

Figure 8-10: TX Low Latency Buffered Mode: Use Model TX_2G . . . . . . . . . . . . . . . . . . 208

Figure 8-11: TX Low Latency Buffered Mode: Use Model TX_2H . . . . . . . . . . . . . . . . . . 209

Figure 8-12: Using PCS TXCLK as Synchronization Clock (Use Models TX_3A-B). . . 210

Figure 8-13: TX Low Latency Buffer Bypass Mode: Use Model TX_3A . . . . . . . . . . . . . 212

Figure 8-14: TX Low Latency Buffer Bypass Mode: Use Model TX_3B. . . . . . . . . . . . . . 213

Figure 8-15: TXSYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 8-16: RX Low Latency Buffered Mode: Use Model RX_1A . . . . . . . . . . . . . . . . . . 221

Figure 8-17: RX Low Latency Buffered Mode: Use Model RX_1B . . . . . . . . . . . . . . . . . . 222

Figure 8-18: RX Low Latency Buffered Mode: Use Model RX_1C . . . . . . . . . . . . . . . . . . 223

Figure 8-19: RX Low Latency Buffer Bypass Mode: Use Model RX_2A . . . . . . . . . . . . . 225

Figure 8-20: RX Low Latency Buffer Bypass Mode: Use Model RX_2B . . . . . . . . . . . . . 226

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UG076 (v4.1) November 2, 2008

Figure 8-21: RX Low Latency Buffer Bypass Mode: Use Model RX_2C . . . . . . . . . . . . . 227

Figure 8-22: RXSYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Section II:

Board Level Design

Chapter 9: Methodology Overview

Figure 9-1: Two RocketIO MGTs Interconnected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Chapter 10: PCB Materials and Traces

Figure 10-1: Differential Edge-Coupled Centered Stripline . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 10-2: Differential Edge-Coupled Offset Stripline. . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 10-3: Centered Broadside-Coupled Stripline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 10-4: Differential Microstrip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Chapter 11: Design of Transitions

Figure 11-1: TDR Signature of Shunt Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 11-2: TDR Signature of Series Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 11-3: Integration of Normalized TDR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 11-4: 2D Field Solver Analysis of 5 Mil Trace and 28 Mil Pad . . . . . . . . . . . . . . . 247

Figure 11-5: Transition Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 11-6: Ansoft HFSS Model of Capacitor with a Pad Clear-Out . . . . . . . . . . . . . . . 248

Figure 11-7: Return Loss Comparison Between 0402 Pad Structures . . . . . . . . . . . . . . . . 248

Figure 11-8: Return Loss Comparison Between 0402 Pad Structures

on Log (Frequency) Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 11-9: TDR Results Comparing 0402 Pad Structures

with Excess Capacitance Reduced from 840 fF to 70 fF . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 11-10: Differential Via Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 11-11: Differential GSSG Via in 16-layer PCB from Pins L11 and L6. . . . . . . . . 251

Figure 11-12: Simulated Return Loss Comparing Differential and Common-Mode

Losses for L11 and L6 GSSG Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 11-13: Example Design for 90 Degree Bends in Traces . . . . . . . . . . . . . . . . . . . . . 252

Figure 11-14: Simulated TDR of 45 Degree Bends with Jog-Outs . . . . . . . . . . . . . . . . . . 253

Figure 11-15: Simulated Return Loss of 45 Degree Bends with Jog-Outs. . . . . . . . . . . . 253

Figure 11-16: Simulated Phase Response of 45 Degree Bends with Jog-Outs . . . . . . . . 254

Figure 11-17: 90° Mitered Turns without and with Jog-Outs. . . . . . . . . . . . . . . . . . . . . . . 254

Figure 11-18: Measured TDR of Differential Pair with Four Mitered 90° Turns,

with and without Jog-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Chapter 12: Guidelines and Examples

Figure 12-1: Differential Via Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 12-2: BGA Escape Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

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