STM32F303C: Arm Cortex-M4 MCU with FPU, High-Performance Memory and peripherals

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"STM32F303CB是一款基于Arm Cortex-M4内核的32位微控制器，集成了浮点单元（FPU），具备256KB的闪存和48KB的SRAM，支持4个ADC、2个DAC通道、7个比较器、4个PGA、多个定时器，工作电压范围为2.0V至3.6V。该芯片适用于全生产阶段，数据手册更新至2018年10月，版本为DS9118 Rev14。" STM32F303CB的主要特点和功能包括： 1. **核心处理器**：采用Arm Cortex-M4 32位处理器，带有浮点单元（FPU），最高可运行在72MHz频率，单周期乘法和硬件除法功能，提供90DMIPS性能，支持数字信号处理指令以及内存保护单元（MPU）。 2. **工作电压与功耗管理**：器件的工作电压范围为2.0V至3.6V，具备电源上电/下电复位（POR/PDR）、可编程电压检测器（PVD）功能，支持睡眠、停止和待机等低功耗模式，还有VBAT供电以供RTC（实时时钟）和备份寄存器使用。 3. **内存配置**：内置128KB至256KB的闪存，最高可达40KB的SRAM，其中前16KB有硬件奇偶校验检查功能。此外，还有一块8KB的SRAM用于指令和数据总线，同样带有硬件奇偶校验（CCM）。 4. **错误检测与安全**：包含CRC计算单元，增强了数据完整性的检查能力。 5. **复位与电源管理**：提供了多种复位机制，如电源复位、程序电压检测器，确保系统在异常情况下能正确响应。 6. **时钟系统**：支持4到32MHz的晶体振荡器，32kHz振荡器用于RTC，并具有校准功能。还包括8MHz的内部RC振荡器和40kHz的内部振荡器，以及倍频选项。 7. **输入/输出接口**：多达87个快速I/O端口，所有端口都可以映射到外部引脚，便于系统扩展和连接各种外设。 8. **模拟功能**：集成4个ADC（模数转换器），2个DAC（数模转换器）通道，7个比较器和4个PGA（可编程增益放大器），这些特性使得STM32F303CB适合于各种模拟信号处理应用。 STM32F323CB因其丰富的外设接口、高性能的处理器核心以及低功耗设计，常应用于工业控制、自动化、物联网设备、医疗设备、消费电子等领域。它的灵活性和强大的处理能力使其成为嵌入式系统设计者的理想选择。

Functional overview STM32F303xB STM32F303xC

16/149 DS9118 Rev 14

3.7 Power management

3.7.1 Power supply schemes

• V

, V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is

provided externally through V

pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators

operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied

to V

DDA

differs from one analog peripheral to another. Table 3 provides the summary of

the V

DDA

ranges for analog peripherals. The V

DDA

voltage level must be always

greater or equal to the V

voltage level and must be provided first.

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when V

is not present.

3.7.2 Power supply supervision

The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.

They are always active, and ensure proper operation above a threshold of 2 V. The device

remains in reset mode when the monitored supply voltage

is below a specified threshold,

POR/PDR, without the need for an external reset circuit.

• The POR monitors only the V

supply voltage. During the startup phase it is required

that V

DDA

should arrive first and be greater than or equal to V

• The PDR monitors both the V

and V

DDA

supply voltages, however the V

DDA

power

supply supervisor can be disabled (by programming a dedicated Option bit) to reduce

the power consumption if the application design ensures that V

DDA

is higher than or

equal to V

The device features an embedded programmable voltage detector (PVD) that monitors the

power supply and compares it to the VPVD threshold. An interrupt can be generated

when V

drops below the V

PVD

threshold and/or when V

is higher than the V

PVD

threshold. The interrupt service routine can then generate a warning message and/or put

the MCU into a safe state. The PVD is enabled by software.

3.7.3 Voltage regulator

The regulator has three operation modes: main (MR), low-power (LPR), and power-down.

• The MR mode is used in the nominal regulation mode (Run)

• The LPR mode is used in Stop mode.

• The power-down mode is used in Standby mode: the regulator output is in high

impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The voltage regulator is always enabled after reset. It is disabled in Standby mode.

Table 3. External analog supply values for analog peripherals

Analog peripheral Minimum V

DDA

supply Maximum V

DDA

supply

ADC / COMP 2.0 V 3.6 V

DAC / OPAMP 2.4 V 3.6V

DS9118 Rev 14 17/149

STM32F303xB STM32F303xC Functional overview

3.7.4 Low-power modes

The STM32F303xB/STM32F303xC supports three low-power modes to achieve the best

compromise between low-power consumption, short startup time and available wakeup

sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC

alarm, COMPx, I2Cx or U(S)ARTx.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin or an RTC alarm occurs.

Note: The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

3.8 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix

Interconnect source

Interconnect

destination

Interconnect action

TIMx

TIMx Timers synchronization or chaining

ADCx

DAC1

Conversion triggers

DMA Memory to memory transfer trigger

Compx Comparator output blanking

COMPx TIMx Timer input: OCREF_CLR input, input capture

ADCx TIMx Timer triggered by analog watchdog

Functional overview STM32F303xB STM32F303xC

20/149 DS9118 Rev 14

3.10 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current

capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allows I/O toggling up to 36 MHz.

3.11 Direct memory access (DMA)

The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-to-

memory and memory-to-peripheral transfers. The DMA controller supports circular buffer

management, avoiding the generation of interrupts when the controller reaches the end of

the buffer.

Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with

software trigger support for each channel. Configuration is done by software and transfer

sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose timers,

DAC and ADC.

3.12 Interrupts and events

3.12.1 Nested vectored interrupt controller (NVIC)

The STM32F303xB/STM32F303xC devices embed a nested vectored interrupt controller

(NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

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